Method for fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-2016163532-A1
Application number	US-201414562768-A
Country	US
Kind code	A1
Filing date	Dec 7, 2014
Priority date	Dec 7, 2014
Publication date	Jun 9, 2016
Grant date	—

Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a hard mask on the gate structure and the ILD layer; forming a first patterned mask layer on the hard mask; using the first patterned mask layer to remove part of the hard mask for forming a patterned hard mask; and utilizing a gas to strip the first patterned mask layer while forming a protective layer on the patterned hard mask, wherein the gas is selected from the group consisting of N 2 and O 2 .

First claim

What is claimed is:

1 . A method for fabricating semiconductor device, comprising:
providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a hard mask on the gate structure and the ILD layer; forming a first patterned mask layer on the hard mask; using the first patterned mask layer to remove part of the hard mask for forming a patterned hard mask; and utilizing a gas to strip the first patterned mask layer while forming a protective layer on the patterned hard mask, wherein the gas is selected from the group consisting of N 2 and O 2 .

2 . The method of claim 1 , wherein the hard mask comprises TiN.

3 . The method of claim 2 , wherein the protective layer comprises TiON or TiO x .

4 . The method of claim 1 , wherein the first patterned mask layer comprises an organic dielectric layer (ODL).

5 . The method of claim 1 , further comprising:
forming an oxide layer on the gate structure and the ILD layer; forming the hard mask and the first patterned mask layer on the oxide layer; stripping the first patterned mask layer and forming the protective layer on the patterned hard mask; and using the patterned hard mask and the protective layer to remove part of the oxide layer and part of the ILD layer for forming a plurality of openings adjacent to the gate structure.

6 . The method of claim 1 , further comprising:
forming an oxide layer on the gate structure and the ILD layer; forming the hard mask and the first patterned mask layer on the oxide layer; stripping the first patterned mask layer and forming the protective layer on the patterned hard mask; forming an ODL on the oxide layer and the protective layer; forming a silicon-containing hard mask bottom anti-reflective coating (SHB) on the ODL; using a patterned resist to remove part of the SHB, part of the ODL, part of the oxide layer, and part of the ILD layer for forming a plurality of openings; and stripping the patterned resist, the SHB, and the ODL.

7 . The method of claim 1 , wherein the patterned hard mask comprises a first pattern and a second pattern, and the first pattern covers the gate structure entirely.

8 . The method of claim 7 , further comprising:
forming a second patterned mask layer on the patterned hard mask, wherein the second patterned mask layer comprises at least a slot opening exposing the second pattern of the patterned hard mask.

Assignees

• United Microelectronics Corp

Inventors

• Lu Chia-Lin
• Chen Chun-Lung
• Liao Kun-Yuan
• Chang Feng-Yi
• Liou En-Chiuan
• Chen Chieh-Te

Classifications

• H10P50/287

  by chemical means · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/2043

  using an anti-reflective coating · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/73 Primary

  using masks for insulating materials · CPC title