Gate contact structure having gate contact layer

Patent metadata

Field	Value
Publication number	US-2016336399-A1
Application number	US-201514712388-A
Country	US
Kind code	A1
Filing date	May 14, 2015
Priority date	May 14, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

There is set forth herein a gate contact structure for a gate. The gate contact structure can include a first contact layer and a second contact layer. In one embodiment, a gate contact layer can define a contact that provides a gate tie down. In one embodiment, a gate contact layer can have a minimum width larger than a gate length.

First claim

1 . A semiconductor structure comprising:
a gate having gate spacers, a gate dielectric layer, and a conductive work function layer; and a contact structure having a first contact layer and a second contact layer, the second contact layer being formed on the first contact layer, wherein the second contact layer provides an electrical connection to a source-drain adjacent to the gate to define a gate tie down structure.

2 . The semiconductor structure of claim 1 , wherein the first contact layer has a top elevation in common with a top elevation of the gate spacers.

3 . The semiconductor structure of claim 1 , wherein the first contact layer is in contact with a conductive section of the gate.

4 . The semiconductor structure of claim 1 , wherein the first contact layer is in contact with a conductive work function layer.

5 . (canceled)

6 . The semiconductor structure of claim 1 , wherein the second contact layer is in contact with a source-drain contact layer adjacent to the gate to define a gate tie down structure.

7 . The semiconductor structure of claim 1 , wherein the second contact layer has a minimum width larger than of gate length of the gate.

8 . The semiconductor structure of claim 1 , wherein the semiconductor structure includes a first logic area and a second logic area, and wherein the contact structure defines a gate tie down structure, the gate tie down structure providing electrical isolation between the first logic area and the second logic area.

9 . A method for fabrication of a semiconductor structure comprising:
providing a gate having gate spacers, a gate dielectric layer and one or more conductive work function layer; and forming a contact structure having a first contact layer and a second contact layer, the second contact layer being formed on the first contact layer, wherein the second contact layer defines a gate tie down electrically connected to a source-drain contact layer.

10 . The method of claim 9 , wherein the first contact layer has a top elevation in common with a top elevation of the gate spacers.

11 . The method of claim 9 , wherein the first contact layer is in contact with a conductive section of the gate.

12 . The method of claim 9 , wherein the first contact layer is in contact with a conductive work function layer.

13 . (canceled)

14 . The method of claim 9 , wherein the second contact layer provides an electrical connection to a source-drain adjacent to the gate to define a gate tie down structure.

15 . The method of claim 9 , wherein the second contact layer is in contact with a source-drain contact layer adjacent to the gate to define a gate tie down structure.

16 . The method of claim 9 , wherein the second contact layer has a minimum width larger than a gate length of the gate.

17 . A semiconductor structure comprising:
a gate having gate spacers, a gate dielectric layer, and a conductive work function layer; and a contact structure having a first contact layer and a second contact layer, the second contact layer being formed on the first contact layer, wherein the second contact layer provides an electrical connection to a source-drain adjacent to the gate to define a gate tie down structure. The semiconductor structure of claim 1 , wherein the semiconductor structure includes a first logic area and a second logic area, and wherein the contact structure defines a gate tie down structure, the gate tie down structure providing electrical isolation between the first logic area and the second logic area.

18 . The semiconductor structure of claim 17 , wherein the second contact layer is in contact with a source-drain contact layer adjacent to the gate to define a gate tie down structure.

Assignees

• Global Foundries Inc
• Globalfoundries Inc

Inventors

• Labonte Andre
• Kim Ryan Ryoung-Han

Classifications

• H10W20/0698 Primary

  Local interconnections · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D30/0275

  forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions · CPC title

• H10D64/259

  Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric · CPC title