Semiconductor device with needle-shaped field plate structures

Patent metadata

Field	Value
Publication number	US-10872957-B2
Application number	US-201916691828-A
Country	US
Kind code	B2
Filing date	Nov 22, 2019
Priority date	Feb 25, 2016
Publication date	Dec 22, 2020
Grant date	Dec 22, 2020

Abstract

A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
a transistor cell region formed in the semiconductor substrate and comprising a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate; and
an inner termination region formed in the semiconductor substrate and devoid of transistor cells, the inner termination region surrounding the transistor cell region and comprising needle-shaped second field plate structures extending from the first surface into the semiconductor substrate,
wherein the first field plate structures and the second field plate structures have the same layout.

2. The semiconductor device of claim 1 , wherein the gate structure forms a grid having meshes with gaps which surround the transistor sections, and wherein connection sections of the semiconductor substrate form bridges between neighboring ones of the transistor sections.

3. The semiconductor device of claim 1 , wherein center-to-center distances between neighboring second field plate structures, between neighboring first and second field plate structures, and between neighboring first field plate structures are equal.

4. The semiconductor device of claim 1 , wherein the gate structure forms a grid having uninterrupted meshes which surround the transistor sections.

5. A semiconductor device, comprising:
a semiconductor substrate;
a transistor cell region formed in the semiconductor substrate and comprising a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate; and
an inner termination region formed in the semiconductor substrate and devoid of transistor cells, the inner termination region surrounding the transistor cell region and comprising needle-shaped second field plate structures extending from the first surface into the semiconductor substrate,
wherein the first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.

6. The semiconductor device of claim 5 , wherein center points of the second field plate structures and center points of the first field plate structures are equally spaced such that the second field plate structures and the first field plate structures complement each other in a regular pattern.

7. The semiconductor device of claim 5 , wherein the gate structure forms a grid having meshes with gaps which surround the transistor sections, and wherein connection sections of the semiconductor substrate form bridges between neighboring ones of the transistor sections.

8. The semiconductor device of claim 5 , wherein center-to-center distances between neighboring second field plate structures, between neighboring first and second field plate structures, and between neighboring first field plate structures are equal.

9. The semiconductor device of claim 5 , wherein an arrangement of center points of the second field plate structures is congruent to an arrangement of center points of a portion of the first field plate structures.

10. The semiconductor device of claim 5 , wherein the gate structure forms a grid having uninterrupted meshes which surround the transistor sections.

11. The semiconductor device of claim 5 , further comprising:
an auxiliary electrode and second contact structures electrically connecting, in the termination region, the auxiliary electrode with second field electrodes in the second field plate structures.

12. The semiconductor device of claim 11 , wherein the auxiliary electrode is electrically connected with a first load electrode that is electrically connected with first field electrodes in the first field plate structures.

13. The semiconductor device of claim 5 , further comprising:
a transition region interposed between the transistor cell region and the inner termination region, the transition region forming a first pn junction with a drift structure of the transistor cell region, the first pn junction extending to the first surface of the semiconductor substrate.

14. The semiconductor device of claim 13 , wherein the first pn junction extends horizontally between neighboring ones of the second field plate structures aligned in a same row, and wherein the second field plate structures in the same row have the same distance to the transistor cell region.

15. The semiconductor device of claim 13 , wherein the transition region comprises connection portions of the gate structure.

16. The semiconductor device of claim 5 , further comprising:
an outer termination region interposed between a lateral outer surface of the semiconductor substrate and an outermost one of the second field plate structures, the lateral outer surface extending from the first surface to a second surface of the semiconductor substrate.

17. The semiconductor device of claim 16 , wherein an outer section of the outer termination region is devoid of regions of a second conductivity type that are spaced from the second surface of the semiconductor substrate and that form pn junctions with a drift structure of the transistor cell region.

18. The semiconductor device of claim 16 , wherein the outer termination region comprises a conductive structure electrically connected to the drift structure.

19. The semiconductor device of claim 18 , wherein the conductive structure comprises a conductive fill of a trench structure extending from the first surface into the semiconductor substrate.

20. The semiconductor device of claim 18 , wherein the conductive structure comprises a heavily doped region directly adjoining the first surface.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Siemieniec Ralf
• Blank Oliver
• Hirler Franz
• Hutzler Michael
• Laforet David
• Ouvrard Cedric
• Yip Li Juin

Classifications

• H10D62/157

  Impurity concentrations or distributions · CPC title

• H10D62/106

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title

• H10D12/461

  having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title