High voltage tolerant bonding pad structure for trench-based semiconductor devices

Patent metadata

Field	Value
Publication number	US-9899343-B2
Application number	US-201615065227-A
Country	US
Kind code	B2
Filing date	Mar 9, 2016
Priority date	Mar 9, 2016
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Apparatus and associated methods relate to a bonding pad structure for a trench-based semiconductor device. The bonding pad structure reduces a peak magnitude of the electric field between a metal bonding pad and the underlying semiconductor. The bonding pad structure includes a plurality of trenches vertically extending from a top surface of a semiconductor. Each of the plurality of trenches has dielectric sidewalls and a dielectric bottom, the dielectric sidewalls and dielectric bottom electrically isolating a conductive core within each of the trenches from a region of semiconductor outside of and adjacent to each of the plurality of trenches. The bonding pad structure includes a metal bonding pad disposed above the plurality of trenches, the metal bonding pad electrically isolated from the region of semiconductor outside of the trenches. The conductive core can be biased to reduce the magnitude of the field between adjacent trenches.

First claim

The invention claimed is:

1. A bonding pad structure for a trench-based semiconductor device comprising:
a plurality of trenches vertically extending from a top surface of a semiconductor, wherein each of the plurality of trenches has dielectric sidewalls and a dielectric bottom, the dielectric sidewalls and dielectric bottom electrically isolating a conductive core within each of the trenches from a region of the semiconductor outside of and adjacent to each of the plurality of trenches, the region of the semiconductor outside of and adjacent to each of the plurality of trenches biased via a contact on a bottom surface of the semiconductor;
a metal bonding pad disposed above the plurality of trenches, the metal bonding pad electrically isolated from the region of the semiconductor outside of and adjacent to each of the plurality of trenches; and
a layer of interconnect metal disposed above the plurality of trenches in a region outside of the metal bonding pad, the layer of interconnect metal contacting each of the plurality of conductive cores so as to provide a voltage bias to each of the plurality of the conductive cores.

2. The bonding pad structure of claim 1 , further comprising:
a dielectric material disposed between the metal bonding pad and the conductive cores of each of the plurality of trenches.

3. The bonding pad structure of claim 1 , wherein the dielectric sidewalls and the dielectric bottom of each of the plurality of trenches comprise silicon-dioxide.

4. The bonding pad structure of claim 1 , wherein each of the conductive cores comprises polysilicon.

5. The bonding pad structure of claim 1 , wherein the plurality of trenches is arranged in a regular array beneath the metal bonding pad.

6. The bonding pad structure of claim 1 , wherein the trench-based semiconductor device is a trench IGBT.

7. The bonding pad structure of claim 1 , wherein the trench-based semiconductor device is a trench MOSFET.

8. The bonding pad structure of claim 7 , wherein each of the plurality of conductive cores is electrically connected to a source of the trench MOSFET.

9. The bonding pad structure of claim 7 , wherein the metal bonding pad is electrically connected to the gate of the trench MOSFET.

10. The bonding pad structure of claim 1 , wherein each of the plurality of trenches is a longitudinal trench having a longitudinal dimension measured from a first longitudinal sidewall to a second longitudinal sidewall that is at least four times greater than a lateral dimension measured from a first lateral sidewall to a second lateral sidewall.

11. The bonding pad structure of claim 10 , wherein each of the plurality of trenches longitudinally extends from a first region outside of the metal bonding pad, underneath the metal bonding pad, and to a second region outside of the metal bonding pad.

12. The bonding pad structure of claim 10 , wherein each of the plurality of trenches is separated from an adjacent one of the plurality of trenches by a common separation distance.

13. The bonding pad structure of claim 10 , wherein a ratio of the lateral dimension of the trenches to a lateral pitch between adjacent trenches is between 0.4 and 0.6.

14. A method of manufacturing a semiconductor device having a bonding pad structure of claim 1 , the method comprising:
etching a plurality of trenches into a semiconductor, each of the plurality of trenches extending from a top surface of the semiconductor, each of the plurality of trenches having sidewalls and a bottom;
lining the sidewalls and the bottom of each of the plurality of trenches with a first dielectric material, the dielectric material isolating an interior cavity from the semiconductor;
depositing a conductive material into each of the interior cavity of each of the plurality of trenches;
providing a second dielectric material within the interior cavity of each of the plurality of trenches;
etching the second dielectric material to expose the conductive material;
depositing a first layer of metal that electrically contacts the conductive material within each of the cavities;
patterning the first layer metal into a plurality of interconnection nets; and
disposing a bonding pad above a portion of the plurality of trenches,
wherein the bonding pad is electrically isolated from both a drain-biased region of semiconductor outside of the trenches and conductive material within the portion of the plurality of trenches.

15. The method of claim 14 , further comprising:
forming gates within a portion of the trenches not underneath the bonding pad.

16. A bonding pad structure for a trench MOSFET comprising:
a semiconductor having a bonding pad region and a region surrounding the bonding pad region;
a plurality of longitudinal trenches, each longitudinal trench having a longitudinal dimension and a lateral dimension, the longitudinal dimension measured from a first longitudinal sidewall to a second longitudinal sidewall, the lateral dimension measured from a first lateral sidewall to a second lateral sidewall, each longitudinal trench vertically extending from a top surface of the semiconductor to a trench bottom, wherein the lateral sidewalls and the trench bottom of each of the plurality of longitudinal trenches have a dielectric layer isolating a conductive core within each of the longitudinal trenches from a drain-biased region of semiconductor outside of and adjacent to the longitudinal trenches;
a layer of interconnect metal disposed above the plurality of longitudinal trenches in the region surrounding the bonding pad region, the layer of interconnect metal contacting each of the plurality of conductive cores; and
a metal bonding pad disposed above the plurality of longitudinal trenches, the metal bonding pad electrically isolated from the layer of interconnect metal and electrically isolated from the drain-biased region of semiconductor outside of and adjacent to the longitudinal trenches.

17. The bonding pad structure of claim 16 , further comprising:
a dielectric material disposed between the metal bonding pad and the conductive cores in the bonding pad region.

18. The bonding pad structure of claim 16 , wherein the conductive core comprises polysilicon.

19. The bonding pad structure of claim 16 , wherein the dielectric layer comprise silicon-dioxide.

20. The bonding pad structure of claim 16 , wherein each of the plurality of conductive cores is electrically connected to a source of the trench MOSFET.

21. The bonding pad structure of claim 16 , wherein the metal bonding pad is electrically connected to the gate of the trench MOSFET.

Assignees

• Polar Semiconductor Llc
• Sanken Electric Co Ltd

Inventors

• West Peter
• Kosier Steven
• Kamimura Tatsuya
• Rankila Don

Classifications

• H10W72/07552

  changes in structures or sizes · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title