Semiconductor device with needle-shaped field plate structures in a transistor cell region and in an inner termination region

Patent metadata

Field	Value
Publication number	US-10510846-B2
Application number	US-201715437191-A
Country	US
Kind code	B2
Filing date	Feb 20, 2017
Priority date	Feb 25, 2016
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a plurality of transistor cells and a gate structure that forms a grid separating transistor sections of the transistor cells from each other, each of the transistor sections including a needle-shaped first field plate structure extending from a first surface into the semiconductor substrate. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The first field plate structures form a first portion of a regular pattern and the second field plate structures form a second portion of the same regular pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor portion comprising a first surface, a second surface opposite the first surface and a drift structure of a first conductivity type disposed between the first and second surfaces;
a transistor cell region comprising needle-shaped first field plate structures extending from the first surface into the semiconductor portion, and body regions of a second conductivity type opposite the first conductivity type surrounding the first field plate structures in a horizontal plane; and
an inner termination region surrounding the transistor cell region and comprising needle-shaped second field plate structures extending from the first surface into the semiconductor portion, the inner termination region being devoid of regions of the second conductivity type that are spaced from the second surface of the semiconductor portion.

2. The semiconductor device of claim 1 , wherein in at least a portion of the inner termination region a center-to-center distance between neighboring ones of the second field plate structures is smaller than a center-to-center distance between neighboring ones of the first field plate structures.

3. The semiconductor device of claim 1 , wherein a center-to-center distance between neighboring ones of the second field plate structures is uniform and equal to a center-to-center distance between neighboring ones of the first field plate structures.

4. The semiconductor device of claim 1 , wherein a mean horizontal cross-sectional area of at least some of the second field plate structures is at least 110% of a mean horizontal cross-sectional area of the first field plate structures.

5. The semiconductor device of claim 1 , wherein on each side of the transistor cell region, the inner termination region comprises at least six rows of second field plate structures.

6. The semiconductor device of claim 1 , wherein on each side of the transistor cell region, the inner termination region comprises at least two rows of the second field plate structures.

7. The semiconductor device of claim 1 , wherein the inner termination region is devoid of doped regions that form unipolar homojunctions with the drift structure.

8. An electronic assembly comprising the semiconductor device of claim 1 .

9. The semiconductor device of claim 1 , further comprising:
a transition region interposed between the transistor cell region and the inner termination region, the transition region comprising a region of the second conductivity type which forms a first pn junction with the drift structure, the first pn junction extending to the first surface of the semiconductor portion.

10. The semiconductor device of claim 9 , wherein the first pn junction extends horizontally between neighboring ones of the second field plate structures aligned in a same row, wherein the second field plate structures in the same row have the same distance to the transistor cell region.

11. The semiconductor device of claim 1 , further comprising:
an auxiliary electrode and second contact structures electrically connecting, in the termination region, the auxiliary electrode with second field electrodes in the second field plate structures.

12. The semiconductor device of claim 11 , wherein the auxiliary electrode is electrically connected with a first load electrode that is electrically connected with first field electrodes in the first field plate structures.

13. The semiconductor device of claim 1 , wherein the body regions of the transistor cell region form first pn junctions with the drift structure, and wherein source regions of the transistor cell region form second pn junctions with the body regions.

14. The semiconductor device of claim 13 , further comprising:
a first load electrode and first contact structures electrically connecting, in the transistor cell region, the first load electrode with the source regions and the body regions.

15. The semiconductor device of claim 14 , wherein the first contact structures electrically connect the first load electrode with first field electrodes in the first field plate structures.

16. The semiconductor device of claim 1 , wherein the transistor cell region comprises a gate structure extending from the first surface into the semiconductor portion, wherein the first field plate structures are formed in meshes of the gate structure.

17. The semiconductor device of claim 16 , further comprising:
a transition region interposed between the transistor cell region and the inner termination region, wherein in the transition region a body region forming a first pn junction with the drift structure directly adjoins the first surface, and wherein the transition region comprises connection portions of the gate structure.

18. The semiconductor device of claim 17 , further comprising:
an interlayer dielectric separating a first load electrode from the semiconductor portion, the interlayer dielectric insulating the first load electrode from the body region in the transition region.

19. The semiconductor device of claim 1 , further comprising:
an outer termination region interposed between a lateral outer surface of the semiconductor portion and an outermost one of the second field plate structures, the lateral outer surface extending from the first surface to the second surface.

20. The semiconductor device of claim 19 , wherein the outer termination region is devoid of regions of the second conductivity type that are spaced from the second surface of the semiconductor portion and that form pn junctions with the drift structure.

21. The semiconductor device of claim 19 , wherein the outer termination region comprises regions of the second conductivity type that are spaced from the second surface of the semiconductor portion and that form pn junctions with the drift structure.

22. The semiconductor device of claim 19 , wherein an inner section of the outer termination region is interposed between the inner termination region, and wherein an outer section of the outer termination region is devoid of regions of the second conductivity type that are spaced from the second surface of the semiconductor portion and that form pn junctions with the drift structure.

23. The semiconductor device of claim 22 , wherein a horizontal width of the inner section parallel to the first surface is at least half of a vertical extension of the second field plate structures.

24. The semiconductor device of claim 19 , wherein the outer termination region comprises a conductive structure electrically connected to the drift structure.

25. The semiconductor device of claim 24 , wherein the conductive structure comprises a conductive fill of a trench structure extending from the first surface into the semiconductor portion.

26. The semiconductor device of claim 24 , wherein the conductive structure comprises a heavily doped region directly adjoining the first surface.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Siemieniec Ralf
• Blank Oliver
• Hirler Franz
• Hutzler Michael
• Laforet David
• Ouvrard Cedric
• Yip Li Juin

Classifications

• H01L29/7396

  Electricity · mapped topic

• H01L29/7811

  Electricity · mapped topic

• H01L29/404 Primary

  Electricity · mapped topic

• H01L29/4238

  Electricity · mapped topic

• H01L29/0638

  Electricity · mapped topic