Error detection code generation circuits of semiconductor devices, memory controllers including the same and semiconductor memory devices including the same

Patent metadata

Field	Value
Publication number	US-10868570-B2
Application number	US-202016747979-A
Country	US
Kind code	B2
Filing date	Jan 21, 2020
Priority date	Dec 2, 2016
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.

First claim

What is claimed is:

1. An error detection code generation circuit providing an error checking mode for a semiconductor memory device, the error detection code generation circuit comprising:
a first cyclic redundancy check (CRC) engine configured to receive first unit data and first data bus inversion bits and to generate first error detection code bits based on the first unit data and the first data bus inversion bits during the error checking mode;
a second CRC engine, during the error checking mode, configured to receive second unit data and second data bus inversion bits and to generate second error detection code bits based on the second unit data and the second data bus inversion bits, the second error detection code bits including a selected bit and remaining unselected bits, the selected bit of the second error detection code bits having a first value in response to a first level of a mode signal and having a second value in response to a second level of the mode signal, and the remaining unselected bits of the second error detection code bits have same values during the error checking mode; and
an XOR circuit configured to receive the first error detection code bits and the second error detection code bits and to output final error detection code bits by performing an exclusive OR function in response to the second level of the mode signal,
wherein the error detection code generation circuit outputs the first error detection code bits and the second error detection code bits in a full rate mode in response to the first level of the mode signal and outputs the final error detection code bits in a half rate mode in response to the second level of the mode signal,
wherein the first error detection code bits are generated by applying a first generation matrix on the first unit data and the first data bus inversion bits, and the second error detection code bits are generated by applying a second generation matrix on the second unit data and the second data bus inversion bits,
the second generation matrix including first matrix elements corresponding to the selected bit of the second error detection code bits and second matrix elements corresponding to remaining unselected bits of the second error detection code bits,
the first matrix elements of the second generation matrix, during the full rate mode, having a first data pattern in response to the first level of the mode signal, the first data pattern being a row of the first matrix elements corresponding to a most significant bit of the second error detection code bits, and during the half rate mode, having a second data pattern in response to the second level of the mode signal, the second data pattern being an inverted version of the row of the first matrix elements corresponding to the most significant bit of the second error detection code bits.

2. The error detection code generation circuit of claim 1 , wherein the second CRC engine includes a multiplexer configured to output the first value of the selected bit in response to the first level of the mode signal and the second value of the selected bit in response to the second level of the mode signal.

3. The error detection code generation circuit of claim 1 , wherein the first data pattern and the second data pattern are complementary.

4. The error detection code generation circuit of claim 1 , wherein, during the half rate mode, the first matrix elements of the second generation matrix are inverted when compared with corresponding matrix elements of the first generation matrix.

5. The error detection code generation circuit of claim 1 , wherein the second value of the selected bit is different from the first value of the selected bit.

6. The error detection code generation circuit of claim 5 , wherein the selected bit is the most significant bit of the second error detection code bits.

7. The error detection code generation circuit of claim 1 , wherein the full rate mode indicates normal data output speed, and the half rate mode indicates half of the normal data output speed.

8. The error detection code generation circuit of claim 1 , wherein the first unit data and the second unit data are sixty-four bits respectively, the first data bus inversion bits and the second data bus inversion bits are eight bits respectively, and the first error detection code bits, second error detection code bits, and the final error detection code bits are eight bits respectively.

9. An error detection code generation circuit providing a first error checking mode and a second error checking mode for a double data rate synchronous dynamic random access memory (DDR SDRAM), the error detection code generation circuit comprising:
a first cyclic redundancy check (CRC) engine configured to receive first unit data and to generate first error detection code bits based on the first unit data and a first generation matrix during both the first error checking mode and the second error checking mode;
a second CRC engine configured to receive second unit data and to generate second error detection code bits based on the second unit data and a second generation matrix, the second error detection code bits including a selected bit and remaining unselected bits, the second generation matrix including first matrix elements corresponding to the selected bit of the second error detection code bits and second matrix elements corresponding to remaining unselected bits of the second error detection code bits, the first matrix elements of the second generation matrix, during the first error checking mode, having a first data pattern in response to a first level of a mode signal, the first data pattern being a row of the first matrix elements corresponding to a most significant bit of the second error detection code bits, and during the second error checking mode, having a second data pattern in response to a second level of the mode signal, the second data pattern being an inverted version of the row of the first matrix elements corresponding to the most significant bit of the second error detection code bits, thereby the selected bit has a first value during the first error checking mode and has a second value during the second error checking mode; and
an XOR circuit configured to receive the first error detection code bits and the second error detection code bits and output final error detection code bits by performing an exclusive OR function during the second error checking mode,
wherein, the error code generation circuit is configured to output the first error detection code bits and the second error detection code bits respectively in a full rate mode during the first error checking mode and to output the final error detection code bits in a half rate mode during the second error checking mode.

10. The error detection code generation circuit of claim 9 , wherein the second CRC engine includes a multiplexer configured to output the first value of the selected bit in response to the first level of the mode signal and the second value of the selected bit in response to the second level of the mode signal respectively.

11. The error detection code generation circuit of claim 10 , wherein the first data pattern and the second data pattern are complementary.

12. The error detection code generation circuit of claim 10 , wherein the second value of the selected bit is different from the first value of the selected bit.

13. The error detection code generation circuit of claim 12 , wherein, during the first error checking mode, the first matrix elements of the second generation matrix are inverted when compared with corresponding matrix elements of the first generation matrix.

14.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cha Sang-Uhn
• Ryu Ye-Sin
• Kim Young-Sik
• Doo Su-Yeon

Classifications

• H03M13/2906 Primary

  using block codes (H03M13/2957 takes precedence) · CPC title

• G06F11/102 Primary

  Error in check bits · CPC title

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• H03M13/09

  Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit · CPC title