Common mode sampling mechanism for residue amplifier in switched current pipeline analog-to-digital converters

Patent metadata

Field	Value
Publication number	US-9503119-B2
Application number	US-201514714602-A
Country	US
Kind code	B2
Filing date	May 18, 2015
Priority date	May 29, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A switched current pipeline analog-to-digital converter (ADC) integrated circuit. The integrated circuit comprises a track and hold circuit (T/H) and a residue amplifier. The T/H is configured to generate a differential output of the T/H based on an analog input. The residue amplifier is coupled to the T/H, configured to capture a sample of a common mode signal of the differential output of the T/H during a periodic pulse interval, wherein the pulse interval is less than half of the time duration of the period of the pulse, configured to generate a corrected input common mode feedback signal based in part on the sample of the common mode signal of the differential output of the T/H, and configured to generate a differential output of the residue amplifier based on the differential output of the T/H and based on the corrected input common mode feedback signal.

First claim

What is claimed is:

1. A switched current pipeline analog-to-digital converter (ADC) integrated circuit, comprising:
a track and hold circuit (T/H) configured to receive an analog input, to receive a T/H clock signal, and to generate a differential output of the T/H based on the analog input and the T/H clock signal; and
a residue amplifier coupled to the T/H and configured to receive a reset clock signal, configured to receive the differential output of the T/H, configured to generate an input common mode signal from the differential output of the T/H, configured to generate a differential output of the residue amplifier, configured to generate an output common mode signal based on the differential output of the residue amplifier, configured to generate a common mode feedback signal based on a difference between the output common mode signal and a corrected input common mode signal, wherein the differential output of the residue amplifier is based on the differential output of the T/H and the common mode feedback signal, configured to generate a sample of the input common mode signal at a periodic rate of the reset clock signal and for a time duration that is less than half of a period of the reset clock signal, and configured to generate the corrected input common mode signal based on the sample of the input common mode signal.

2. The integrated circuit of claim 1 , wherein the residue amplifier is configured to operate when receiving a reset clock signal having a fundamental frequency of at least 350 megahertz (MHz).

3. The integrated circuit of claim 1 , wherein the residue amplifier comprises a sample and hold circuit that is configured to generate the sample of the input common mode signal.

4. The integrated circuit of claim 3 , wherein the sample and hold circuit comprises a pulse generator circuit that is configured to generate a pulse at the periodic rate of the reset clock signal, wherein the pulse has a time duration of less than half the period of the reset clock signal.

5. The integrated circuit of claim 4 , wherein the sample and hold circuit comprises:
a first buffer amplifier that that is configured to receive the input common mode signal,
an electronic switch having an input coupled to an output of the first buffer amplifier and having a control input coupled to an output of the pulse generator circuit,
a capacitor coupled to an output of the electronic switch, and
a second buffer amplifier having an input coupled to the output of the electronic switch and to the capacitor,
wherein the sample and hold circuit is configured to track the input common mode signal when the pulse generated by the pulse generator circuit is active and to hold a previous value of the input common mode signal when the pulse generated by the pulse generator circuit is inactive, and
wherein the sample and hold circuit is configured to generate the corrected input common mode signal as an output of the second buffer amplifier.

6. The integrated circuit of claim 4 , wherein the pulse generator circuit comprises:
a delay component configured to receive the reset clock signal and to output a delayed reset clock signal,
an inverter configured to receive the delayed reset clock signal and to output an inverted delayed reset clock signal, and
an AND gate configured to receive the reset clock signal at a first input of the AND gate, configured to receive the inverted delayed reset clock signal at a second input of the AND gate, and to generate the pulse based on the reset clock signal and based on the inverted delayed reset clock signal.

7. The integrated circuit of claim 1 , wherein the integrated circuit is used in one of a mobile communication device, a video player, a set top box, an application specific integrated circuit (ASIC), or a mixed signal device.

8. A method, comprising:
generating, by a residue amplifier of a switched current pipeline analog-to-digital converter (ADC) integrated circuit, a differential output of the residue amplifier based on a reset clock signal, based on a differential output of a track and hold circuit (T/H), and based on a common mode feedback signal;
generating, by the residue amplifier, a corrected input common mode signal by sampling an input common mode signal at a periodic rate of the reset clock signal and for a time duration that is less than half of a period of the reset clock signal; and
generating, by the residue amplifier, the common mode feedback signal based on a difference between an output common mode signal and the corrected input common mode signal.

9. The method of claim 8 , further comprising:
receiving, by the T/H, an analog input;
receiving, by the T/H, the reset clock signal;
generating, by the T/H, the differential output of the T/H based on the analog input and the reset clock signal.

10. The method of claim 9 , further comprising generating, by the residue amplifier, the input common mode signal from the differential output of the T/H.

11. The method of claim 10 , wherein the input common mode signal has a step component associated with a charge injection mechanism in the T/H.

12. The method of claim 11 , wherein the input common mode signal is sampled during a time duration when the step component is absent from the input common mode signal.

13. The method of claim 12 , further comprising generating a pulse based on the reset clock signal, wherein the pulse has a fundamental frequency that is the same as the fundamental frequency of the reset clock signal, wherein the pulse is active when the step component is absent from the input common mode signal, and wherein the pulse controls the sampling of the input common mode signal.

14. The method of claim 8 , wherein the reset clock signal has a fundamental frequency of at least 350 megahertz (MHz).

15. A switched current pipeline analog-to-digital converter (ADC) integrated circuit, comprising:
a track and hold circuit (T/H) configured to generate a differential output of the T/H based on an analog input; and
a residue amplifier coupled to the T/H, configured to capture a sample of a common mode signal of the differential output of the T/H during a periodic pulse interval, wherein the pulse interval is less than half of the time duration of the period of the pulse, configured to generate a corrected input common mode feedback signal based in part on the sample of the common mode signal of the differential output of the T/H, and configured to generate a differential output of the residue amplifier based on the differential output of the T/H and based on the corrected input common mode feedback signal.

16. The integrated circuit of claim 15 , wherein the residue amplifier comprises a sample and hold circuit configured to sample the common mode signal of the differential output of the T/H when a step component is absent from the common mode signal of the differential output of the T/H and configured to output the corrected input common mode feedback signal.

17. The integrated circuit of claim 16 , wherein the sample and hold circuit comprises a pulse generator that controls the sampling of the common mode signal of the differential output of the residue amplifier.

18. The integrated circuit of claim 17 , wherein the pulse generator is configured to generate a pulse based on the reset clock signal and based on an inverted delayed reset clock signal.

19. The integrated circuit of claim 18 , wherein the pulse generator is configured to generate the inverted delayed reset clock signal based on the reset clock signal.

20.

Assignees

• Texas Instruments Inc

Inventors

• Coulon Jesse
• El-Chammas Manar
• Li Xiaopeng
• Kimura Shigenobu

Classifications

• H03M1/44

  Sequential comparisons in series-connected stages with change in value of analogue signal · CPC title

• H03F2203/45431

  the CMCL output control signal being a current signal · CPC title

• H03F3/45565

  Controlling the active amplifying circuit of the differential amplifier · CPC title

• H03F2203/45396

  the AAC comprising one or more switches · CPC title

• H03M1/0607

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title