Variable gain amplifier utilizing positive feedback and time-domain calibration

Patent metadata

Field	Value
Publication number	US-10284145-B2
Application number	US-201715803081-A
Country	US
Kind code	B2
Filing date	Nov 3, 2017
Priority date	Nov 3, 2016
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A variable gain amplifier utilizing positive feedback and time-domain calibration includes an integration phase and a regeneration phase. A current source provides a bias current that increases linearity in the integration phase and reduces common-mode voltage dependence. The circuit includes a timing control loop, wherein a variable gain of a residue amplifier is proportional to a first time that a timing control loop signal is kept high, as determined by an on or off status of respectively paired inverter assemblies each having an input voltage determined by an amplifier output voltage during the regeneration phase. A strong-arm latch structure acts as a positive feedback latch until the first time is de-asserted.

First claim

What is claimed is:

1. A variable gain amplifier utilizing positive feedback and time-domain calibration comprising:
an integration phase, wherein the integration phase reduces input-referred noise and offset, and provides increased linearity;
a regeneration phase, wherein the regeneration phase provides high-speed amplification;
a current source, wherein the current source provides a bias current that increases linearity in the integration phase, reduces common-mode voltage dependence, and provides a dynamic mechanism to trade-off noise and linearity for speed;
a timing control loop, wherein a variable gain of a residue amplifier is proportional to a time τ amp that a timing control loop signal, clka, is kept high, as determined by an on or off status of respectively paired inverter assemblies each having an input voltage determined by an amplifier output voltage during the regeneration phase; and
a strong-arm latch structure, wherein once the amplifier is in the regeneration phase, said strong arm latch acts as a positive feedback latch until clka is deasserted,
wherein the variable gain amplifier utilizing positive feedback and time-domain calibration consumes no static power.

2. The variable gain amplifier utilizing positive feedback and time domain calibration of claim 1 , wherein the integration phase comprises transistors M 1 , M 2 , M 3 , M 4 , PMOS transistors M 5 and M 6 , current source M 13 and nodes V xp /V xn , C x , V op /V on , and Vbias, wherein during the integration phase, a differential current through transistors M 1 and M 2 is initially integrated on a capacitance at the nodes V xp /V xn , C x , and once the Vx node voltages decrease enough to turn on transistors M 3 and M 4 , the differential current is then integrated onto an output load until the voltage at nodes V op /V on drops below a threshold voltage of positive feedback PMOS transistors M 5 and M 6 .

3. The variable gain amplifier utilizing positive feedback and time domain calibration of claim 2 , wherein the amplifier is used as a comparator between a first stage and a second stage of a SAR ADC.

4. The variable gain amplifier utilizing positive feedback and time domain calibration of claim 3 , wherein when the clka signal is low, capacitance of the second stage of the SAR ADC is disconnected from the amplifier and the amplifier behaves as a normal comparator.

5. The variable gain amplifier utilizing positive feedback and time domain calibration of claim 3 , wherein the output load comprises a parallel combination of the second stage ADC capacitance, C s2 , and parasitic capacitance of the comparator, C o .

6. The variable gain amplifier utilizing positive feedback and time domain calibration of claim 5 , wherein gain at the end of the integration phase, G int , approximately comprises

G
int

≈

(

ℊ
m

I
D

)

1
,
2

⁢

⁢

{

V

T
⁢

⁢
5

,
6

+

C
X

C

s
⁢

⁢
2

+

C
0

⁢

(

V

T
⁢

⁢
5

,
6

+

V

T
⁢

⁢
3

,
4

)

}

.

7. The variable gain amplifier utilizing positive feedback and time domain calibration of claim 6 , wherein at the end of the regeneration phase, the total amplifier gain, G, is approximately G≈G int ·e T regen /τ, where T regen is the total regeneration time and τ is the regeneration time constant, given by

τ
≈

C

s
⁢

⁢
2

+

C
0

ℊ

m
⁢

⁢
5

,
6

.

Assignees

• Univ Texas

Inventors

• Sun Nan
• Gandara Miguel

Classifications

• H03M1/10

  Calibration or testing · CPC title

• H03K3/35613

  the input circuit having a differential configuration · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03M1/14

  Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit · CPC title

• H03F1/08

  Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements (wide-band amplifiers with inter-stage coupling networks incorporating these impedances H03F1/42) · CPC title