Successive approximation sigma delta analog-to-digital converters

Patent metadata

Field	Value
Publication number	US-9660662-B2
Application number	US-201615210051-A
Country	US
Kind code	B2
Filing date	Jul 14, 2016
Priority date	Jul 8, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

An A/D converter including first and second A/D converters and a recombination module. The first A/D converter receives an analog input signal, converts the analog input signal to a first digital signal, and includes a successive approximation module, which performs a successive approximation to generate the first digital signal. The second A/D converter converts an analog output of the first A/D converter to a second digital signal. The analog output of the first A/D converter is generated based on the analog input signal. The second A/D converter is a fine conversion A/D converter relative to the first A/D converter. The second A/D converter performs the delta-sigma conversion process and includes a decimation filter that suppresses noise which reduces amplification and power consumption requirements of the first A/D converter and performs a delta-sigma decimation process to generate the second digital signal based on the analog output of the first A/D converter.

First claim

What is claimed is:

1. An analog-to-digital converter comprising:
a first analog-to-digital converter configured to receive an analog input signal and convert the analog input signal to a first digital signal, the first analog-to-digital converter comprising a successive approximation module, wherein the successive approximation module is configured to perform a successive approximation to generate the first digital signal;
a second analog-to-digital converter configured to convert an analog output of the first-analog-to-digital converter to a second digital signal, wherein the analog output of the first analog-to-digital converter is generated based on the analog input signal, wherein the second analog-to-digital converter is a fine conversion analog-to-digital converter relative to the first analog-to-digital converter, wherein the second analog-to-digital converter performs the delta-sigma conversion process and comprises a decimation filter, and wherein the decimation filter is configured to
suppress noise which reduces amplification and power consumption requirements of the first analog-to-digital converter, and
perform a delta-sigma decimation process to generate the second digital signal based on the analog output of the first analog-to-digital converter; and

a combination module configured to combine the first digital signal and the second digital signal to provide a resultant output signal.

2. The analog-to-digital converter of claim 1 , wherein the second analog-to-digital converter comprises:
a digital-to-analog converter,
a subtractor configured to receive the output of the first analog-to-digital converter and an output of the digital-to-analog converter,
a comparator configured to receive an output of the subtractor and a first reference voltage, wherein the comparator comprises
a loop filter configured to filter the output of the subtractor, and
a latch configured to receive an output of the loop filter, and

wherein the decimation filter is configured to filter and perform the delta-sigma decimation process to generate the second digital signal based on an output of the latch, wherein the output of the second digital-to-analog converter is generated based on the second digital signal.

3. The analog-to-digital converter of claim 1 , wherein the first analog-to-digital converter comprises:
a first digital-to-analog converter,
a first subtractor configured to receive a sample and hold signal and an output of the first digital-to-analog converter, and
a first comparator configured to compare an output of the first subtractor with a first reference voltage,
wherein the successive approximation module is configured to perform the successive approximation to generate the first digital signal based on an output of the first comparator, wherein the output of the first digital-to-analog converter is generated based on the first digital signal.

4. The analog-to-digital converter of claim 3 , wherein the first digital-to-analog converter comprises a charge sharing digital-to-analog converter or a charge redistribution digital-to-analog converter configuration.

5. The analog-to-digital converter of claim 3 , wherein the second analog-to-digital converter comprises:
a second digital-to-analog converter,
a second subtractor configured to receive the output of the first subtractor and an output of the second digital-to-analog converter,
a second comparator configured to receive an output of the second subtractor and the first reference voltage, wherein the second comparator comprises
a loop filter configured to filter the output of the subtractor, and
a latch configured to receive an output of the loop filter, and

wherein the decimation filter is configured to perform the delta-sigma decimation process to generate the second digital signal based on an output of the latch, wherein the output of the second digital-to-analog converter is generated based on the second digital signal.

6. The analog-to-digital converter of claim 5 , wherein:
the first analog-to-digital converter is configured to, for a plurality of cycles, generate the first digital signal based on the sample and hold signal; and
the second analog-to-digital converter is configured to generate the second digital signal based on a difference between (i) the sample and hold signal and (ii) a result of a successive approximation performed subsequent to the plurality of cycles,
wherein the second analog-to-digital converter does not generate the second digital signal during the plurality of cycles.

7. The analog-to-digital converter of claim 5 , wherein:
the first digital-to-analog converter is configured to convert a first most-significant-bit of a plurality of bits to be converted to an analog output signal;
the first digital-to-analog converter comprises a first plurality of capacitors;
the first plurality of capacitors of the a first digital-to-analog converter are charged by a plurality of reference voltages during a sampling phase of the analog signal;
the plurality of reference voltages includes the first reference voltage;
charges of the first plurality of capacitors of the first digital-to-analog converter are shared during successive approximations of a first one or more bits of the first digital signal;
the second digital-to-analog converter is configured to convert a first least-significant-bit of the plurality of bits to be converted to the analog output signal;
the second digital-to-analog converter comprises a second plurality of capacitors;
the second plurality of capacitors of the second digital-to-analog converter are charged based on a common mode voltage during the sampling phase of the analog output signal; and
the second digital-to-analog converter is configured to perform charge redistribution by connecting the second plurality of capacitors of the second digital-to-analog converter to receive the plurality of reference voltages during successive approximations of a second one or more bits of the first digital signal.

8. A method comprising:
receiving an analog input signal and converting the analog input signal to a first digital signal at a first analog-to-digital converter;
performing a successive approximation to generate the first digital signal via the first analog-to-digital converter;
converting an analog output of the first analog-to-digital converter to a second digital signal via a second analog-to-digital converter, wherein the second analog-to-digital converter is a fine conversion analog-to-digital converter relative to the first analog-to-digital converter;
suppressing noise of the second analog-to-digital converter via a decimation filter;
performing a delta-sigma conversion via the second analog-to-digital converter to generate the second digital signal based on the analog output of the first analog-to-digital converter, wherein the analog output of the first digital-to-analog converter is generated based on the analog input signal; and
combining the first digital signal and the second digital signal to provide a resultant output signal.

9. The method of claim 8 , further comprising:
receiving a sample and hold signal and an output of a first digital-to-analog converter at a first subtractor;
comparing an output of the first subtractor with a first reference voltage at a first comparator, wherein the first analog-to-digital converter comprises the first subtractor, the first comparator and the first analog-to-digital converter; and
performing the successive approximation to generate the first digital signal based on an output of the first comparator, wherein the output of the first digital-to-analog converter is generated based on the first digital signal.

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Assignees

• Marvell World Trade Ltd
• Marvell World Tradte Ltd

Inventors

• Venca Alessandro
• Nani Claudio
• Ghittori Nicola
• Bosi Alessandro

Classifications

• H03M1/667 Primary

  Recirculation type · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/462 Primary

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/804

  with charge redistribution · CPC title

• H03M1/08

  of noise {(H03M1/0617 takes precedence)} · CPC title