3D semiconductor devices including a supporter and methods of forming the same

Patent metadata

Field	Value
Publication number	US-10868041-B2
Application number	US-202016843460-A
Country	US
Kind code	B2
Filing date	Apr 8, 2020
Priority date	May 21, 2018
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

A semiconductor device comprises a lower conductive layer on a substrate. A conductive line is on the lower conductive layer. A buried trench in the conductive line is provided. A supporter which is on the conductive line and extends in the buried trench is provided. A stack structure including a plurality of insulating layers and a plurality of conductive layers that are alternately stacked is on the supporter. A channel structure passing through the stack structure, the supporter, and the conductive line is provided. An isolation trench passing through the stack structure, the supporter, and the conductive line is provided.

First claim

What is claimed is:

1. A semiconductor device comprising:
a lower conductive layer on a substrate;
a conductive line on the lower conductive layer;
a buried trench in the conductive line;
a supporter on the conductive line and extending in the buried trench;
a stack structure comprising a plurality of insulating layers and a plurality of conductive layers that are alternately stacked on the supporter;
a channel structure that passes through the stack structure, the supporter, and the conductive line; and
an isolation trench that passes through the stack structure, the supporter, and the conductive line,
wherein the buried trench is spaced apart from the isolation trench.

2. The semiconductor device of claim 1 , wherein the supporter comprises:
a support plate on the conductive line; and
a support bar in the buried trench and connected with the support plate.

3. The semiconductor device of claim 2 , wherein the isolation trench is spaced apart from the support bar.

4. A method of forming a semiconductor device, comprising:
forming a lower conductive layer on a substrate;
forming a mold layer on the lower conductive layer;
forming a trench in the mold layer;
forming a supporter on the mold layer and extending in the trench;
forming a preliminary stack structure comprising a plurality of insulating layers and a plurality of sacrificial layers that are alternately stacked on the supporter;
forming a channel structure passing through the preliminary stack structure, the supporter, and the mold layer;
forming an isolation trench passing through the preliminary stack structure, the supporter, and the mold layer;
removing the mold layer to form a cavity;
forming a conductive line in the cavity;
removing the plurality of sacrificial layers to form a plurality of gap regions; and
forming a plurality of conductive layers in the plurality of gap regions,
wherein the plurality of insulating layers and the plurality of conductive layers that are alternately stacked on the supporter constitute a stack structure.

5. The method of forming the semiconductor device of claim 4 , wherein the supporter comprises:
a support plate on the conductive line; and
a support pattern in the trench and configured to connect with the support plate.

6. The method of forming the semiconductor device of claim 5 , wherein the isolation trench passes through the support pattern.

7. The method of forming the semiconductor device of claim 5 , wherein the support pattern comprises a same material as the support plate.

8. The method of forming the semiconductor device of claim 5 , wherein the support pattern and the support plate comprise polysilicon.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Sang Jun
• Kim Ee Jou
• Shin Joong Shik

Classifications

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B41/41

  of a memory region comprising a cell select transistor, e.g. NAND · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title