Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same

Patent metadata

Field	Value
Publication number	US-9917100-B2
Application number	US-201615354116-A
Country	US
Kind code	B2
Filing date	Nov 17, 2016
Priority date	Nov 20, 2015
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. A source conductive line structure is provided between the substrate and the alternating stack. The source conductive line structure includes a plurality of parallel conductive rail structures extending along a same horizontal direction and adjoined to a common conductive straddling structure. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support matrix. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure and the support matrix.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of electrically conductive layers and insulating layers located over a substrate;
an array of memory stack structures, each memory stack structure extending through the alternating stack and including a memory film and a semiconductor channel laterally surrounded by the memory film;
a source conductive layer contacting a bottom portion of a sidewall of each semiconductor channel and located between the alternating stack and the substrate, wherein the source conductive layer comprises a plurality of conductive rail structures extending along a first horizontal direction and laterally spaced from one another; and
a support structure comprising a matrix material layer and laterally surrounding a bottom portion of each of the memory stack structures,
wherein the source conductive layer further comprises a conductive straddling structure extending along a second horizontal direction that is different from the first horizontal direction, wherein each of the conductive rail structures is adjoined to the conductive straddling structure, and
wherein the three-dimensional memory device comprises at least one feature selected from:
a first feature that a convex sidewall of each semiconductor channel contacts a concave sidewall of a respective conductive rail structure, wherein an azimuthal angle between two vertical edges of a contact area between the convex sidewall and the respective conductive rail structure as measured around a vertical axis passing through a geometrical center of a memory stack structure including the semiconductor channel is in a range from 45 degrees to 270 degrees;
a second feature that the matrix material layer comprises a first doped semiconductor material and is electrically shorted to the source conductive layer, and an entirety of the source conductive layer is an integral structure that continuously extends throughout each portion of the source conductive layer and comprises a second doped semiconductor material having a same conductivity type as the first doped semiconductor material; and
a third feature that each sidewall of the plurality of conductive rail structures comprises a set of planar vertical sidewall portions adjoined among one another by a set of concave vertical sidewall portions, each of the planar vertical sidewall portions contacts the matrix material layer, each of the concave vertical sidewall portions contacts a respective semiconductor channel, and an entirety of the bottom surfaces of the plurality of conductive rail structures contacts recessed surfaces of the matrix material layer that is located above a horizontal plane including a bottom surface of the matrix material layer.

2. The three-dimensional memory device of claim 1 , wherein:
the plurality of conductive rail structures are located in a plurality of channels in the matrix material layer that extend along the first horizontal direction; and
a convex sidewall and a bottom surface of each memory film contacts the matrix material layer.

3. The three-dimensional memory device of claim 1 , wherein the three-dimensional memory device comprises the first feature.

4. The three-dimensional memory device of claim 1 , wherein the three-dimensional memory device comprises the second feature.

5. The three-dimensional memory device of claim 1 , wherein the three-dimensional memory device comprises the third feature.

6. The three-dimensional memory device of claim 1 , wherein the conductive straddling structure overlies each of the plurality of conductive rail structures, is adjoined to a top portion of each of the plurality of conductive rail structures, and comprises a same conductive material as the plurality of conductive rail structures.

7. The three-dimensional memory device of claim 6 , further comprising a plurality of bit lines extending in a bit line direction, wherein the electrically conductive layers comprise word lines which extend in a word line direction perpendicular to the bit line direction.

8. The three-dimensional memory device of claim 7 , wherein:
the first horizontal direction differs from both the word line direction and the bit line direction; and
the conductive straddling structure extends in the word line direction.

9. The three-dimensional memory device of claim 7 , wherein:
the first horizontal direction is parallel to the bit line direction; and
the conductive straddling structure extends in the word line direction.

10. The three-dimensional memory device of claim 1 , further comprising:
a source connection layer located between the plurality of conductive rail structures and the alternating stack, contacting a sidewall of the conductive straddling structure, and laterally surrounding the memory stack structures; and
a dielectric separator structure comprising a dielectric material, vertically extending through an entirety of the alternating stack, and overlying an entire area of the conductive straddling structure.

11. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a vertical NAND device located over the substrate;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device;
the substrate comprises a silicon substrate;
the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;
the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

12. A three-dimensional memory device comprising:
an alternating stack of electrically conductive layers and insulating layers located over a substrate;
an array of memory stack structures, each memory stack structure extending through the alternating stack and including a memory film and a semiconductor channel laterally surrounded by the memory film;
a source conductive layer contacting a bottom portion of a sidewall of each semiconductor channel and located between the alternating stack and the substrate, wherein the source conductive layer comprises a plurality of conductive rail structures extending along a first horizontal direction and laterally spaced from one another;
a plurality of bit lines extending in a bit line direction, wherein the electrically conductive layers comprise word lines which extend in a word line direction perpendicular to the bit line direction,

wherein:
the source conductive layer further comprises a conductive straddling structure extending along a second horizontal direction that is different from the first horizontal direction, where

Assignees

• Sandisk Technologies Llc

Inventors

• Zhang Tong
• Alsmeier Johann
• Kai James
• Liu Jin
• Zhang Yanli

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H01L27/11519

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic