Vertical type semiconductor devices and methods of manufacturing the same
US-2024172441-A1 · May 23, 2024 · US
Nonvolatile memory device and method for fabricating the same
US9306040B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9306040-B2 |
| Application number | US-201313944120-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 17, 2013 |
| Priority date | Apr 9, 2013 |
| Publication date | Apr 5, 2016 |
| Grant date | Apr 5, 2016 |
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Abstract
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A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.
First claim
Opening claim text (preview).
What is claimed is: 1. A nonvolatile memory device comprising: a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and the second word line formation areas; a first stacked structure and a second stacked structure, each having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein, wherein the first stacked structure and the secon…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D30/693Primary
Electricity · mapped topic
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- What does patent US9306040B2 cover?
- A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality…
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D30/693. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).