Semiconductor device gate structure and method of fabricating thereof

Patent metadata

Field	Value
Publication number	US-10867806-B2
Application number	US-201916556531-A
Country	US
Kind code	B2
Filing date	Aug 30, 2019
Priority date	Nov 18, 2016
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.

First claim

What is claimed is:

1. A method, comprising:
forming a gate structure of a FinFET device, wherein the forming the gate structure includes:
depositing a high-k dielectric layer;
forming a metal layer over the high-k dielectric layer, wherein the metal layer includes fluorine and a metal;
driving fluorine from the metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer;
forming at least one work function layer over the passivated high-k dielectric layer; and
forming a fill metal layer over the at least one work function layer.

2. The method of claim 1 , further comprising:
forming a metal nitride layer over the high-k dielectric layer and underlying the metal layer.

3. The method of claim 2 , further comprising:
prior to forming the metal nitride layer, forming another metal nitride layer over the high-k dielectric layer.

4. The method of claim 1 , wherein the forming the metal layer is performed by atomic layer deposition (ALD).

5. The method of claim 4 , wherein precursors to the ALD provide a metal precursor and a fluorine precursor.

6. The method of claim 5 , wherein the metal is tungsten.

7. The method of claim 1 , wherein the forming the metal layer is performed by chemical vapor deposition (CVD).

8. The method of claim 1 , wherein the metal layer is formed using a precursor including tungsten.

9. A method of forming a gate structure of a semiconductor device, comprising:
depositing a gate dielectric layer over a substrate, wherein the gate dielectric layer includes oxygen vacancies;
forming a metal layer over the gate dielectric layer, wherein the metal layer includes a first metal and fluorine;
driving fluorine from the metal layer into the gate dielectric layer, wherein the fluorine fills the oxygen vacancies;
removing the metal layer after the driving the fluorine; and
after the removing, forming at least one work function layer over the gate dielectric layer.

10. The method of claim 9 , wherein the driving the fluorine is performed in a nitrogen atmosphere.

11. The method of claim 9 , further comprising: driving nitrogen to fill at least a portion of the oxygen vacancies.

12. The method of claim 9 , further comprising:
forming a metal nitride layer under the metal layer; and
driving nitrogen from the metal nitride layer towards the gate dielectric layer.

13. The method of claim 12 , wherein a thickness of the gate dielectric layer is the same before and after the driving the fluorine.

14. The method of claim 9 , wherein the gate dielectric layer includes a high-k dielectric material.

15. A method of forming a gate structure of a semiconductor device, comprising:
depositing a gate dielectric layer over a substrate;
forming a first layer over the gate dielectric layer;
forming a second layer over the first layer, wherein the second layer includes a first metal and fluorine;
driving fluorine from the second layer into the gate dielectric layer; and
after the driving, forming at least one work function layer over the gate dielectric layer.

16. The method of claim 15 , wherein the first layer is TaN.

17. The method of claim 15 , wherein the first layer is TiN.

18. The method of claim 15 , wherein the forming the second layer includes introducing a precursor including tungsten.

19. The method of claim 18 , wherein the forming the second layer includes atomic layer deposition.

20. The method of claim 15 , further comprising driving nitrogen from the first layer to the gate dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiang Hsin-Che
• Tzeng Ju-Yuan
• Liang Chun-Sheng
• Wang Shu-Hui
• Pan Kuo-Hua

Classifications

• H10P14/69393

  the material containing tantalum, e.g. Ta2O5 · CPC title

• H10P14/6518

  by introduction of substances into an already-existing insulating layer · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/0134 Primary

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title