Semiconductor device with tunable work function

Patent metadata

Field	Value
Publication number	US-9548372-B2
Application number	US-201514609138-A
Country	US
Kind code	B2
Filing date	Jan 29, 2015
Priority date	Jan 29, 2015
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

The metal-oxide semiconductor structure includes a substrate, a gate dielectric multi-layer, an etch stop layer, a work function metallic layer, a barrier layer and a silicide layer. The substrate has a trench. The gate dielectric multi-layer overlies the trench, in which the gate dielectric multi-layer includes a high-k capping layer with a fluorine concentration substantially in a range from 1 at % to 10 at %. The etch stop layer is disposed on the gate dielectric multi-layer. The work function metallic layer is disposed on the etch stop layer. The barrier layer is disposed on the work function metallic layer. The silicide layer is disposed on the barrier layer.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
providing a substrate with a first region and a second region, wherein a first dummy poly gate and a second dummy poly gate are formed in the first region and the second region respectively;
removing the first dummy poly gate and the second dummy poly gate to form a first trench and a second trench;
forming a gate dielectric multi-layer on the first region and the second region, wherein the gate dielectric multi-layer includes a high-k capping layer;
forming an etch stop layer on the gate dielectric multi-layer;
forming a sacrificial layer on the etch stop layer, wherein the sacrificial layer is formed from titanium nitride and has a predetermined crystalline orientation ratio of [200] to [111];
performing a thermal treatment using tungsten hexafluoride on the sacrificial layer on the first region, thereby enabling the high-k capping layer on the first region to have a fluorine concentration substantially in a range from 1 at % to 10 at %;
removing the sacrificial layer to expose the etch stop layer;
forming a first-type work function metallic layer on the etch stop layer on the first region;
forming a second-type work function metallic layer on the etch stop layer on the second region and on the first-type work function metallic layer;
forming a barrier layer on the second-type work function metallic layer; and
forming a silicide layer on the barrier layer.

2. The method of claim 1 , wherein after forming the silicide layer on the barrier layer, the method further comprises performing a chemical mechanical polishing operation on the first region and the second region.

3. The method of claim 1 , wherein performing the thermal treatment on the sacrificial layer on the first region further comprises:
forming a dielectric material on the sacrificial layer;
patterning the dielectric material to expose the sacrificial layer on the first region;
performing the tungsten hexafluoride thermal treatment on the sacrificial layer on the first region and the dielectric material on the second region; and
removing the dielectric material on the second region.

4. The method of claim 1 , wherein forming the first-type work function metallic layer on the etch stop layer on the first region further comprises:
forming the first-type work function metallic layer on the etch stop layer;
forming a dielectric material on the first-type work function metallic layer;
patterning the dielectric material to expose the first-type work function metallic layer on the second region;
removing the first-type work function metallic layer on the second region; and
removing the dielectric material on the first region.

5. The method of claim 1 , wherein forming the gate dielectric multi-layer comprises:
forming an interfacial layer on the first region and the second region;
forming a high-k dielectric layer on the interfacial layer; and
forming the high-k capping layer on the high-k dielectric layer.

6. The method of claim 1 , wherein forming the first-type work function metallic layer on the etch stop layer on the first region further comprises forming a p-type work function metallic layer on the etch stop layer on the first region.

7. The method of claim 1 , wherein forming the second-type work function metallic layer on the etch stop layer on the second region and on the first-type work function metallic layer further comprises forming a n-type work function metallic layer on the etch stop layer on the second region and on the first-type work function metallic layer.

8. The method of claim 1 , wherein performing the tungsten hexafluoride thermal treatment further comprises performing the tungsten hexafluoride thermal treatment with a process temperature substantially in a range from 400° C. to 450° C.

9. The method of claim 1 , wherein forming the sacrificial layer on the etch stop layer further comprises forming the sacrificial layer having the predetermined crystalline orientation ratio of to [111] substantially in a range from 0.66 to 0.92.

10. A method for fabricating a semiconductor device, comprising:
providing a substrate with a first region and a second region;
forming a first trench and a second trench in the first region and the second region respectively;
forming a gate dielectric multi-layer on the first region and the second region, wherein the gate dielectric multi-layer comprises a high-k capping layer;
forming an etch stop layer on the gate dielectric multi-layer;
forming a sacrificial layer on the etch stop layer, wherein the sacrificial layer is formed to have a predetermined crystalline orientation ratio of [200] to [111];
performing a thermal treatment using tungsten hexafluoride on the sacrificial layer on the first region, thereby enabling the high-k capping layer on the first region to have a fluorine concentration substantially in a range from 1 at % to 10 at %;
removing the sacrificial layer to expose the etch stop layer;
forming a first-type work function metallic layer on the etch stop layer on the first region;
forming a second-type work function metallic layer on the etch stop layer on the second region and on the first-type work function metallic layer;
forming a barrier layer on the second-type work function metallic layer; and
forming a silicide layer on the barrier layer.

11. The method of claim 10 , wherein forming the gate dielectric multi-layer comprises:
forming an interfacial layer on the first region and the second region;
forming a high-k dielectric layer on the interfacial layer; and
forming the high-k capping layer on the high-k dielectric layer.

12. The method of claim 10 , wherein forming the sacrificial layer further comprises forming the sacrificial layer from titanium nitride.

13. The method of claim 10 , wherein forming the sacrificial layer on the etch stop layer further comprises forming the sacrificial layer having the predetermined crystalline orientation ratio of [200] to substantially in a range from 0.66 to 0.92.

14. The method of claim 10 , wherein performing the thermal treatment on the sacrificial layer on the first region further comprises:
forming a dielectric material on the sacrificial layer on the second region;
performing the tungsten hexafluoride thermal treatment on the sacrificial layer on the first region and the dielectric material on the second region; and
removing the dielectric material on the second region.

15. The method of claim 10 , wherein performing the tungsten hexafluoride thermal treatment further comprises performing the tungsten hexafluoride thermal treatment with a process temperature substantially in a range from 400° C. to 450° C.

16. The method of claim 10 , wherein forming the first-type work function metallic layer on the etch stop layer on the first region further comprises:
forming the first-type work function metallic layer on the etch stop layer;
forming a dielectric material on the first-type work function metallic layer on the first region;
removing the first-type work function metallic layer on the second region; and
removing the dielectric material on the first region.

17. The method of claim 10 , wherein forming the first-type work function metallic layer on the etch stop layer on the first region further comprises forming a p-type work function metallic layer on the etch stop layer on the first region.

18. The method of claim 10 , wherein forming the second-type work function metallic layer on the etch stop layer on the second region and on the fi

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Chung-Liang
• Chen Wei-Jen
• Chen Yen-Yu
• Zhang Wei

Classifications

• H01L29/4236

  Electricity · mapped topic

• H01L29/511 Primary

  Electricity · mapped topic

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D84/0181

  Manufacturing their gate insulating layers · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title