Method for core and in/out-put device reliability improve at high-K last process

Patent metadata

Field	Value
Publication number	US-9502403-B2
Application number	US-201414169146-A
Country	US
Kind code	B2
Filing date	Jan 30, 2014
Priority date	Jul 30, 2013
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A method for fabricating a semiconductor device includes providing a semiconductor substrate, forming on the semiconductor substrate a dummy gate interface layer and a dummy gate of a core device and a gate interface layer and a dummy gate of an IO device, removing the dummy gates of the core and IO devices, removing the dummy gate interface layer of the core device, forming a gate interface layer in the original location of the removed dummy gate interface layer, forming a high-k dielectric layer each on the gate interface layer of the core and IO devices, and submitting the semiconductor substrate to a high-pressure fluorine annealing. The high-pressure fluorine annealing causes the gate interface layer and the high-k dielectric layer of the core and IO devices to be doped with fluoride ions.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
providing a semiconductor substrate;
forming on the semiconductor substrate a dummy gate interface layer and a dummy gate of a core device and a gate interface layer and a dummy gate of an IO device;
removing the dummy gate of the core device and the dummy gate of the IO device;
removing the dummy gate interface layer of the core device;
forming a gate interface layer in the original location of the removed dummy gate interface layer;
submitting the semiconductor substrate to a first high-pressure fluorine annealing process to cause fluoride ions to be implanted into the gate interface layer of the core device and the gate interface layer of the IO device;
forming a high-k dielectric layer each directly on the gate interface layer of the core device and directly on the gate interface layer of the IO device,
submitting the semiconductor substrate to a second high-pressure fluorine annealing process under a pressure greater than one atmospheric pressure to cause fluoride ions to be implanted onto the high-k dielectric layer of the core device and the high-k dielectric layer of the IO device.

2. The method of claim 1 , wherein the gate interface layer is an oxide layer, the oxide layer being formed by oxidizing the semiconductor substrate.

3. The method of claim 1 , wherein the dummy gate of the core device and the dummy gate of the TO device each are polysilicon.

4. The method of claim 1 , wherein the dummy gate interface layer of the core device and the gate interface layer of the TO device are formed in a same process.

5. The method of claim 1 , wherein removing the dummy gate of the core device and the dummy gate of the TO device comprises a wet etching or a dry etching followed by a wet etching.

6. The method of claim 1 , wherein removing the dummy gate interface layer of the core device comprises a dry etching or a wet etching.

7. The method of claim 1 , wherein forming a gate interface layer in the original location of the removed dummy gate interface layer comprises a chemical oxidation process or a thermal oxidation process.

8. The method of claim 1 , prior to removing the dummy gate interface layer, further comprising:
forming a protective layer covering the gate interface layer of the TO device; and
removing the protective layer after forming the gate interface layer in the original location of the removed dummy gate interface layer.

9. The method of claim 1 , wherein the first high-pressure fluorine annealing is performed at a temperature in a range between 350° C. and 500° C.

10. The method of claim 1 , wherein the first high-pressure fluorine annealing is performed with a time duration of greater than or equal to 5 minutes.

11. The method of claim 1 , wherein the first high-pressure fluorine annealing is performed under the pressure less than or equal to 25 standard atmospheric pressure.

12. The method of claim 1 , wherein the high-k dielectric layer of the core device and the high-k dielectric layer of the TO device each have a U-shaped cross-section.

13. The method of claim 10 , further comprising:
forming a work function on the high-k dielectric layer of the core device and a work function on the high-k dielectric layer of the TO device; and
forming a metal gate on the work function of the core device and a metal gate on the work function of the TO device.

14. The method of claim 1 , wherein the dummy gate of the core device and the dummy gate of the IO device are formed in a same process.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Xie Xinyun

Classifications

• H10D64/01348

  with substrate doping, e.g. N, Ge or C implantation, before formation of the insulator · CPC title

• H10D64/01338

  with a treatment, e.g. annealing, after the formation of the conductor · CPC title

• H10D84/0144 Primary

  Manufacturing their gate insulating layers · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title