Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch

Patent metadata

Field	Value
Publication number	US-10861950-B2
Application number	US-201816121427-A
Country	US
Kind code	B2
Filing date	Sep 4, 2018
Priority date	Nov 16, 2017
Publication date	Dec 8, 2020
Grant date	Dec 8, 2020

Abstract

A field effect transistor including a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, a drain contact on the drain region, and recesses in the source and drain contacts substantially aligned with the gate contact. Upper surfaces of the recesses in the source and drain contacts are spaced below an upper surface of the gate by a depth.

First claim

What is claimed is:

1. A field effect transistor comprising:
a source region;
a drain region;
a channel region extending between the source region and the drain region;
a gate on the channel region;
a gate contact on the gate at an active region of the gate;
a source contact on the source region;
a drain contact on the drain region; and
recesses in the source and drain contacts substantially aligned with the gate contact,
wherein upper surfaces of the recesses in the source and drain contacts are spaced below an upper surface of the gate by a depth, and
wherein the recesses in the source and drain contacts are entirely filled with a dielectric material.

2. The field effect transistor of claim 1 , wherein the recesses are provided in the source and drain contacts only at positions proximate to the gate contact.

3. The field effect transistor of claim 1 , wherein the depth is from approximately 10 nm to approximately 40 nm.

4. The field effect transistor of claim 1 , wherein a length of each of the recesses along a lengthwise direction of the source and drain regions is at least as long as a length of the gate contact along a lengthwise direction of the gate.

5. The field effect transistor of claim 1 , further comprising a via on the source contact or the drain contact, wherein the via is staggered relative to the gate contact.

6. The field effect transistor of claim 5 , wherein the via is longitudinally offset from the gate contact in a lengthwise direction of the source contact or the drain contact by a distance from approximately 10 nm to approximately 25 nm.

7. An integrated circuit comprising:
a plurality of field effect transistors, each field effect transistor comprising:
a source region;
a drain region;
a channel region extending between the source region and the drain region;
a gate on the channel region;
a gate contact on the gate at an active region of the gate;
a source contact on the source region;
a drain contact on the drain region; and
recesses in the source and drain contacts substantially aligned with the gate contact,
wherein upper surfaces of the recesses in the source and drain contacts are spaced below an upper surface of the gate by a depth, and
wherein the recesses in the source and drain contacts are entirely filled with a dielectric material.

8. The integrated circuit of claim 7 , wherein, for each field effect transistor of the plurality of field effect transistors, the recesses are provided in the source and drain contacts only at positions proximate to the gate contact.

9. The integrated circuit of claim 7 , wherein, for each field effect transistor of the plurality of field effect transistors, the depth is from approximately 10 nm to approximately 40 nm.

10. The integrated circuit of claim 7 , wherein, for each field effect transistor of the plurality of field effect transistors, a length of each of the recesses along a lengthwise direction of the source and drain regions is at least as long as a length of the gate contact along a lengthwise direction of the gate.

11. The integrated circuit of claim 7 , wherein each field effect transistor of the plurality of field effect transistors further comprises a via on the source contact or the drain contact, and wherein the via is staggered relative to the gate contact.

12. The integrated circuit of claim 8 , wherein the via is longitudinally offset from the gate contact in a lengthwise direction of the source contact or the drain contact by a distance from approximately 10 nm to approximately 25 nm.

13. The integrated circuit of claim 7 , further comprising a shallow trench isolation region between a first field effect transistor of the plurality of field effect transistors and a second field effect transistor of the plurality of field effect transistors.

14. An integrated circuit comprising:
a plurality of field effect transistors, each field effect transistor comprising:
a source region;
a drain region;
a channel region extending between the source region and the drain region;
a gate on the channel region;
a gate contact on the gate at an active region of the gate;
a source contact on the source region;
a drain contact on the drain region; and
recesses in the source and drain contacts substantially aligned with the gate contact,
wherein upper surfaces of the recesses in the source and drain contacts are spaced below an upper surface of the gate by a depth; and

a shallow trench isolation region between a first field effect transistor of the plurality of field effect transistors and a second field effect transistor of the plurality of field effect transistors,
wherein the source region or the drain region of one of the plurality of field effect transistors extends across the shallow trench isolation region and connects the first field effect transistor to the second field effect transistor.

15. The integrated circuit of claim 14 , wherein the via of one of the first and second field effect transistors is at the shallow trench isolation region, and wherein an upper surface of the source region or the drain region that extends across the shallow trench isolation regions includes a notch.

16. The integrated circuit of claim 7 , further comprising:
at least one power rail at a boundary of the integrated circuit; and
a via connecting the source contact of one of the plurality of field effect transistors to the at least one power rail.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Sengupta Rwik
• Rodder Mark
• Hong Joon Goo
• Rakshit Titash

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/40 Primary

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/907

  CMOS gate arrays · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title