MOSFET with asymmetric self-aligned contact

US9484306B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9484306-B1
Application numberUS-201514943663-A
CountryUS
Kind codeB1
Filing dateNov 17, 2015
Priority dateNov 17, 2015
Publication dateNov 1, 2016
Grant dateNov 1, 2016

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a source and drain on a substrate; a first and second gate on the source, and the second gate and a third gate on the drain; a source contact over the source and between the first and second gates, the source contact including first and second portions, the first portion in contact with the source and extending between the first and second gates, and the second portion contacting the first portion and extending over the first and second gates; and a drain contact formed over the drain and between the second and third gates, the drain contact including first and second portions, the first portion contacting the drain, extending between second and third gates, and recessed with respect to the first portion of the source contact, and the second portion in contact with the first portion and extending between and over the second and third gates.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising: a source and a drain formed in a substrate; a first gate and a second gate disposed on the source, and the second gate and a third gate disposed on the drain; a source contact formed over the source and between the first gate and the second gate, the source contact comprising a first portion and a second portion, the first portion being in contact with the source and extending between the first gate and second gate, and the second portion contacting the first portion and extending over the first gate and the second gate; and a drain contact formed over the drain and between the second gate and the third gate, the drain contact comprising a first portion and a second portion, the first portion positioned in contact with the drain, extending between the second gate and the third gate, and recessed with respect to the first portion of the source contact such that the first portion of the source contact has a thickness that is greater than a thickness of the first portion of the drain contact, the second portion positioned in contact with the first portion and extending between and over the second gate and the third gate, and the second portion of the source contact has a thickness than is smaller than the second portion of the drain contact. 2. The semiconductor device of claim 1 , wherein the first portion of the source contact has a thickness in a range from about 20 to about 40 nm, and the first portion of the drain contact has a thickness in a range from about 40 to about 100 nm. 3. The semiconductor device of claim 1 , wherein the first portion of the drain contact is recessed to a level below the second gate and the third gate. 4. The semiconductor device of claim 1 , wherein the second portion of the drain contact has a length that is less than the length of the second portion of the source contact. 5. The semiconductor device of claim 1 , wherein the second portion of the drain contact has a length in a range from about 20 to about 50 nm, and the second portion of the source contact has a length in a range from about 50 to about 500 nm. 6. A semiconductor device, comprising: a source and a drain formed in a substrate; a first gate and a second gate disposed on the source, the second gate and a third gate disposed on the drain, and the first gate, the second gate, and the third gate each having a spacer arranged on a sidewall; a source contact formed over the source and between the first gate and the second gate, the source contact comprising a first portion and a second portion, the first portion being in contact with the source and extending from the spacer of the first gate to the spacer of the second gate, and the second portion contacting the first portion and extending over and contacting the spacer of the first gate and the spacer of the second gate; and a drain contact formed over the drain and between the second gate and the third gate, the drain contact comprising a first portion and a second portion, the first portion positioned in contact with the drain, extending from the spacer of the second gate to the spacer of the third gate, and recessed with respect to the first portion of the source contact such that the first portion of the source contact has a thickness that is greater than a thickness of the first portion of the drain contact, the second portion positioned in contact with the first portion over a central region of the first portion, extending between the second gate and the third gate from the spacer of the second gate to the spacer of the third gate, and extending over and contacting the spacer of the second gate and the spacer of the third gate; wherein the second portion of the source contact has a thickness than is smaller than the second portion of the drain contact.

Assignees

Inventors

Classifications

  • based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

  • Layouts of interconnections · CPC title

  • Local interconnections · CPC title

  • Cross-sectional shapes or dispositions of interconnections · CPC title

  • using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

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Frequently asked questions

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What does patent US9484306B1 cover?
A semiconductor device includes a source and drain on a substrate; a first and second gate on the source, and the second gate and a third gate on the drain; a source contact over the source and between the first and second gates, the source contact including first and second portions, the first portion in contact with the source and extending between the first and second gates, and the second p…
Who is the assignee on this patent?
IBM, Globalfoundries Inc, Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification H10D84/0186. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).