Method of forming semiconductor device including source/drain contact having height below gate stack

Patent metadata

Field	Value
Publication number	US-9478636-B2
Application number	US-201414280196-A
Country	US
Kind code	B2
Filing date	May 16, 2014
Priority date	May 16, 2014
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

Provided is a semiconductor device and methods of forming the same. The semiconductor device includes a substrate having source/drain regions and a channel region between the source/drain regions; a gate structure over the substrate and adjacent to the channel region; source/drain contacts over the source/drain regions and electrically connecting to the source/drain regions; and a contact protection layer over the source/drain contacts. The gate structure includes a gate stack and a spacer. A top surface of the source/drain contacts is lower than a top surface of the spacer, which is substantially co-planar with a top surface of the contact protection layer. The contact protection layer prevents accidental shorts between the gate stack and the source/drain regions when gate vias are formed over the gate stack. Therefore, gate vias may be formed over any portion of the gate stack, even in areas that overlap the channel region from a top view.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
providing a substrate with a gate stack formed thereon, the substrate having a source region, a drain region, and a channel region between the source and drain regions, the gate stack being disposed above the channel region, a top surface and sidewalls of the gate stack being covered by a spacer;
forming a first contact feature over the substrate, the first contact feature electrically connecting to at least one of the source region and the drain region, a top surface of the first contact feature being lower than a top surface of the spacer;
forming a first dielectric layer over the first contact feature;
forming a recess in the spacer thereby exposing the top surface of the gate stack; and
forming a gate open conductor in the recess, wherein the gate open conductor does not physically contact the first dielectric layer.

2. The method of claim 1 , wherein forming the first contact feature includes:
depositing a first conductive material over the substrate and over the spacer; and
performing an etching process selectively tuned to remove the first conductive material while the spacer remains until a top surface of the first conductive material is lower than the top surface of the spacer, leaving a remaining portion of the first conductive material as the first contact feature.

3. The method of claim 1 , wherein forming the first dielectric layer includes:
depositing a first dielectric material over the substrate, the first contact feature, and the spacer; and
performing a chemical-mechanical planarization (CMP) process to the first dielectric material thereby exposing the top surface of the spacer.

4. The method of claim 1 , wherein the forming of the recess includes: performing a first anisotropic etching process to the spacer thereby exposing the top surface of the gate stack, resulting in the recess over the top surface of the gate stack and surrounded by the spacer of the gate stack, wherein the first anisotropic etching process is selectively tuned to remove the spacer while the first dielectric layer substantially remains.

5. The method of claim 4 , wherein forming the gate open conductor includes:
depositing a second conductive material filling the recess and over the first dielectric layer; and
performing a chemical-mechanical planarization (CMP) process to the second conductive material thereby exposing the top surface of the first dielectric layer, resulting in a remaining portion of the second conductive material in the recess as the gate open conductor.

6. The method of claim 4 , further comprising:
depositing a second dielectric layer over the first dielectric layer and the gate open conductor;
forming an opening through at least the second dielectric layer, the opening exposing a top surface of the gate open conductor; and
forming a via in the opening, the via electrically contacting the gate open conductor.

7. The method of claim 6 , wherein the via overlaps the channel region from a top view.

8. The method of claim 4 , further comprising:
depositing a second dielectric layer over the first dielectric layer and the gate open conductor;
forming a first opening through at least the second and first dielectric layers, the first opening exposing the first contact feature; and
forming a second contact feature in the first opening, the second contact feature electrically connecting the first contact feature to another semiconductor device.

9. The method of claim 8 , wherein forming the second contact feature includes:
forming a barrier layer on sidewalls of the first opening, wherein the first contact feature is still exposed through a first space in the first opening;
filling the first space with a third conductive material;
etching back a portion of the third conductive material, resulting in a second space defined by a top surface of the third conductive material and sidewalls of the barrier layer; and
filling the second space with a material substantially matching the barrier layer.

10. The method of claim 8 , further comprising:
forming a second opening through at least the second dielectric layer thereby exposing a top surface of the gate open conductor; and
forming a via in the second opening electrically contacting the gate open conductor, wherein the via overlaps the channel region from a top view.

11. A method of forming a semiconductor device, the method comprising:
providing a substrate having a first active region and a second active region, the first and second active regions being spaced apart by a non-active region;
forming gate structures over the first and second active regions, wherein each of the gate structures includes a gate stack, a spacer covering top and sidewalls of the gate stack, a recess in the spacer, the recess exposing the top of the gate stack, and a gate open conductor in the recess;
forming source/drain regions in the first and second active regions, the source/drain regions adjacent to the gate structures;
forming source/drain contacts over the source/drain regions, a top surface of the source/drain contacts is lower than a top surface of the gate structures; and
forming a contact protection layer over the source/drain contacts, a top surface of the contact protection layer being substantially co-planar with the top surface of the gate structures, wherein the gate open conductor in each of the gate structures does not overlap in plan view with the contact protection layer.

12. The method of claim 11 , wherein forming the source/drain contacts includes:
depositing a first conductive material over the source/drain regions, the first conductive material electrically contacting the source/drain regions; and
etching back the first conductive material until a top surface of the first conductive material is below the top surface of the gate structures, leaving remaining portions of the first conductive material as the source/drain contacts.

13. The method of claim 11 , further comprising:
depositing a dielectric layer over the gate structures and over the contact protection layer; and
forming gate vias through at least the dielectric layer, the gate vias electrically contacting the gate structures, wherein at least one of the gate vias is in one of the first and second active regions from a top view.

14. The method of claim 11 , further comprising:
depositing a first dielectric layer over the gate structures and over the contact protection layer;
etching an opening through the first dielectric layer and the contact protection layer between two of the gate structures, the opening exposing a first one of the source/drain contacts in the first active region and a second one of the source/drain contacts in the second active region; and
forming a contact feature in the opening, the contact feature electrically connecting the first one of the source/drain contacts and the second one of the source/drain contacts.

15. The method of claim 14 , further comprising:
depositing a second dielectric layer over the first dielectric layer and over the contact feature; and
forming gate vias through at least the first and second dielectric layers, the gate vias electrically contacting the gate structures, wherein at least one of the gate vias is in one of the first and second active regions from a top view.

16. A method of forming a semiconductor device, the method comprising:
providing a substrate having a source region, a drain region, and a channel region between the source and drain regions;
forming a gate structure over the sub

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chih-Liang
• Lai Chih-Ming
• Sio Kam-Tou
• Liu Ru-Gun
• Shen Meng-Hung
• Liou Chun-Hung
• Sung Shu-Hui
• Young Charles Chew-Yuen

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/092

  by smoothing the dielectric parts · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title