Composite spacer enabling uniform doping in recessed fin devices

Patent metadata

Field	Value
Publication number	US-10854733-B2
Application number	US-201815957212-A
Country	US
Kind code	B2
Filing date	Apr 19, 2018
Priority date	Sep 2, 2015
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

A semiconductor device that includes at least one fin structure and a gate structure present on a channel portion of the fin structure. An epitaxial semiconductor material is present on at least one of a source region portion and a drain region portion on the fin structure. The epitaxial semiconductor material includes a first portion having a substantially conformal thickness on a lower portion of the fin structure sidewall and a second portion having a substantially diamond shape that is present on an upper surface of the source portion and drain portion of the fin structure. A spacer present on first portion of the epitaxial semiconductor material.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of fin structures;
an epitaxial semiconductor material on at least one of a source region portion and a drain region portion of at least two fin structures that are adjacent in the plurality of fin structures, wherein the epitaxial semiconductor material on each of the at least two fin structures includes a first portion having a uniform thickness on a fin structure sidewall of the source portion and the drain portion of the fin structure and a second portion having a diamond shape that is in direct contact with an upper surface of the source portion and the drain portion of the fin structure, wherein the epitaxial semiconductor material on a first of the fin structures that are adjacent does not contact the epitaxial semiconductor material on a second of the fin structures, the epitaxial semiconductor material being doped to an n-type or p-type dopant that has a substantially uniform concentration along a height of the source and drain portions of the fin structure; and
spacers in direct contact with an entirety of a sidewall of the first portion of the epitaxial semiconductor material.

2. The semiconductor device of claim 1 , wherein the spacer comprises a low-k dielectric material.

3. A semiconductor device comprising;
a plurality of fin structures;
a gate structure present on a channel portion of each of the plurality of fin structures;
an epitaxial semiconductor material on at least one of a source region portion and a drain region portion of the at least two fin structures that are adjacent in the plurality of fin structures, wherein the epitaxial semiconductor material includes a first portion having a uniform thickness on a fin structure sidewall of the source portion and the drain portion of the fin structures, and a second portion having a diamond shape that is in direct contact with an upper surface of the source portion and the drain portion of the fin structures, wherein the epitaxial semiconductor material on a first of the fin structures that are adjacent does not contact the epitaxial semiconductor material on a second of the fin structures, the epitaxial semiconductor being doped to an n-type or p-type dopant that has a substantially uniform concentration along a height of the source and drain portion of the fin structure; and
a spacer present on first portion of the epitaxial semiconductor material, wherein the first portion of the epitaxial semiconductor material is positioned between the spacer and a fin structure for each fin structure in said plurality of fin structures.

4. The semiconductor device of claim 3 , wherein the spacer comprises a low-k dielectric material.

5. A semiconductor device comprising;
an epitaxial semiconductor material on at least one of a source region portion and a drain region portion of the at least one fin structure, wherein the epitaxial semiconductor material includes a first portion on a lower portion of the fin structure sidewall and a second portion having a diamond shape that is present on an upper surface of said at least one of the source portion and drain portion of the fin structures, the epitaxial semiconductor being doped to an n-type or p-type dopant that has a substantially uniform composition along a height of the source and drain portions of the fin structure; and
a spacer present on first portion of the epitaxial semiconductor material, the first portion of the epitaxial semiconductor material positioned between the spacer and the fin structure sidewall to provide that the first portion of the epitaxial semiconductor material has a uniform width.

6. The semiconductor device of claim 5 , wherein the epitaxial semiconductor material in non-merged epitaxial semiconductor material.

7. The semiconductor device of claim 5 , wherein the spacer is present on half a height of the fin structure or less.

8. The semiconductor device of claim 5 , wherein the spacer comprises a low-k dielectric material.

Assignees

• IBM

Inventors

• Basker Veeraraghavan S
• Liu Zuoguang
• Yamashita Tenko
• Yeh Chun-Chen

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P34/42

  with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title