Integrated components which have both horizontally-oriented transistors and vertically-oriented transistors

Patent metadata

Field	Value
Publication number	US-10854617-B2
Application number	US-201916379365-A
Country	US
Kind code	B2
Filing date	Apr 9, 2019
Priority date	Apr 9, 2019
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

Some embodiments include an integrated assembly. The integrated assembly has a first transistor with a horizontally-extending channel region between a first source/drain region and a second source/drain region; has a second transistor with a vertically-extending channel region between a third source/drain region and a fourth source/drain region; and has a capacitor between the first and second transistors. The capacitor has a first electrode, a second electrode, and an insulative material between the first and second electrodes. The first electrode is electrically connected with the first source/drain region, and the second electrode is electrically connected with the third source/drain region. A digit line is electrically connected with the second source/drain region. A conductive structure is electrically connected with the fourth source/drain region.

First claim

We claim:

1. An integrated assembly, comprising:
a first transistor having a horizontally-extending channel region between a first source/drain region and a second source/drain region;
a second transistor having a vertically-extending channel region between a third source/drain region and a fourth source/drain region, the vertically-extending channel region, the third source/drain region and the fourth source/drain region being disposed within a semiconductor pillar;
a capacitor having a first electrode, a second electrode, and an insulative material between the first and second electrodes; the first electrode being electrically connected with the first source/drain region and the second electrode being electrically connected with the third source/drain region and being in direct physical contact with the semiconductor pillar;
a digit line electrically connected with the second source/drain region; and
a conductive structure electrically connected with the fourth source/drain region.

2. The integrated assembly of claim 1 wherein:
the first transistor, the second transistor and the capacitor are comprised by a memory device;
the memory device is one of many substantially identical memory devices within a memory array; and
the conductive structure is electrically connected to the fourth source/drain regions of a plurality of the memory devices.

3. The integrated assembly of claim 2 wherein the memory devices are two-transistor-one-capacitor (2T-1C) memory devices.

4. The integrated assembly of claim 2 wherein the insulative material comprises ferroelectric material; and wherein the memory devices are ferroelectric memory devices.

5. The integrated assembly of claim 1 wherein:
the first transistor, the second transistor and the capacitor are comprised by a first memory device;
a second memory device is adjacent to the first memory device;
the second memory device comprises a third transistor having a horizontally-extending channel region, a fourth transistor having a vertically-extending channel region, and a second capacitor between the third and fourth transistors; and
the second source/drain region is shared between the first transistor and the third transistor.

6. The integrated assembly of claim 5 wherein the conductive structure is electrically coupled with the second memory device through a source/drain region of the fourth transistor.

7. The integrated assembly of claim 6 wherein:
the first and second memory devices are two-transistor-one-capacitor (2T-1C) memory devices;
the digit line is a first comparative digit line; and
the conductive structure is a second comparative digit line which is comparatively coupled to the first comparative digit line through a sense amplifier.

8. The integrated assembly of claim 6 wherein the first and second memory devices are ferroelectric memory devices, and wherein the conductive structure is a plate structure which is electrically connected with a plate driver.

9. An integrated assembly, comprising:
a first transistor having a horizontally-extending channel region between a first source/drain region and a second source/drain region;
a second transistor having a vertically-extending channel region between a third source/drain region and a fourth source/drain region;
a capacitor having a first electrode, a second electrode, and an insulative material between the first and second electrodes; the first electrode being electrically connected with the first source/drain region and the second electrode being electrically connected with the third source/drain region, the first transistor, the second transistor and the capacitor all being comprised by a first memory device;
a digit line electrically connected with the second source/drain region; and
a conductive structure electrically connected with the fourth source/drain region;
a second memory device is adjacent to the first memory device;
the second memory device comprising a third transistor having a horizontally-extending channel region, a fourth transistor having a vertically-extending channel region, and a second capacitor between the third and fourth transistors; and
the second source/drain region being shared between the first transistor and the third transistor, and wherein the conductive structure is not electrically coupled with the second memory device.

10. The integrated assembly of claim 9 wherein the first and second memory devices are ferroelectric memory devices, and wherein the conductive structure is a plate structure which is electrically connected with a plate driver.

11. The integrated assembly of claim 5 wherein:
the second transistor has a second gate transistor gate;
the fourth transistor has a fourth transistor gate; and
the second and fourth transistor gates are electrically coupled to a MUX line.

12. The integrated assembly of claim 5 wherein:
the second transistor has a second gate transistor gate;
the fourth transistor has a fourth transistor gate; and
the second transistor gate is electrically coupled to a first MUX line; and
the fourth transistor gate is electrically coupled to a second MUX line.

13. The integrated assembly of claim 5 wherein:
the first transistor has a first transistor gate;
the second transistor has a second gate transistor gate;
the third transistor has a third transistor gate;
the fourth transistor has a fourth transistor gate;
the first and second transistor gates are electrically coupled with one another; and
the third and fourth transistor gates are electrically coupled with one another.

14. The integrated assembly of claim 5 wherein:
the first transistor has a first transistor gate;
the second transistor has a second gate transistor gate;
the third transistor has a third transistor gate;
the fourth transistor has a fourth transistor gate;
the first transistor gate is electrically coupled with a first wordline which is electrically connected with a wordline driver;
the third transistor gate is electrically coupled with a second wordline which is electrically connected with the wordline driver; and
the second and fourth transistor gates are electrically coupled with a MUX line which is electrically connected with the wordline driver.

15. The integrated assembly of claim 5 wherein:
the first transistor has a first transistor gate;
the second transistor has a second gate transistor gate;
the third transistor has a third transistor gate;
the fourth transistor has a fourth transistor gate;
the first transistor gate is electrically coupled with a first wordline which is electrically connected with a wordline driver;
the third transistor gate is electrically coupled with a second wordline which is electrically connected with the wordline driver; and
the second transistor gate is electrically coupled with a first MUX line which is electrically connected with the wordline driver; and
the fourth transistor gate is electrically coupled with a second MUX line which is electrically connected with the wordline driver.

16. Integrated memory, comprising:
ferroelectric memory devices within a memory array; the ferroelectric memory devices being in paired arrangements, with each paired arrangement comprising a first ferroelectric memory device and a second ferroelectric memory device; each of the first ferroelectric memory devices including a first transistor having a horizontally-extending first channel region, a second transistor having a vertically-extending second channel region, and a first capacitor between the first and second transistors; each of the second ferroelectric me

Assignees

• Micron Technology Inc

Inventors

• Derner Scott J
• Ingalls Charles L

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D30/63 Primary

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title