Integrated Memory Comprising Secondary Access Devices Between Digit Lines and Primary Access Devices

Patent metadata

Field	Value
Publication number	US-2020051982-A1
Application number	US-201916514693-A
Country	US
Kind code	A1
Filing date	Jul 17, 2019
Priority date	Aug 10, 2018
Publication date	Feb 13, 2020
Grant date	—

Abstract

Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

First claim

I/We claim:

1 . An integrated assembly, comprising:
a primary access transistor having a first source/drain region and a second source/drain region which are coupled to one another when the primary access transistor is in an ON mode, and which are not coupled to one another when the primary access transistor is in an OFF mode; a charge-storage device coupled with the first source/drain region; and a digit line coupled with the second source/drain region through a secondary access device; the secondary access device having an ON mode and an OFF mode; the digit line being coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

2 . The integrated assembly of claim 1 wherein the secondary access device is a secondary access transistor.

3 . The integrated assembly of claim 2 wherein:
the primary access transistor has a first channel region which extends horizontally between the first and second source/drain regions; and
the secondary access transistor has a second channel region which extends vertically between a third source/drain region and a fourth source/drain region.

4 . The integrated assembly of claim 1 wherein the charge-storage device is a capacitor.

5 . The integrated assembly of claim 1 wherein the primary access transistor and the charge-storage device together comprise a memory cell, and wherein the memory cell is one of many substantially identical memory cells within a DRAM array.

6 . The integrated assembly of claim 5 wherein the digit line is one of many digit lines extending along columns of the DRAM array, and wherein at least some of the digit lines extend to a common sense amplifier.

7 . An integrated assembly, comprising:
a first primary access transistor and a second primary access transistor, the first primary access transistor comprising a first gate proximate a first channel region, and the second primary access transistor comprising a second gate proximate a second channel region; the first and second primary access transistors together comprising three source/drain regions; the three source/drain regions being a first source/drain region, a second source/drain region and a third source/drain region; the first and second source/drain regions being gatedly coupled to one another through the first channel region; the second and third source/drain regions being gatedly coupled to one another through the second channel region; a first charge-storage device coupled with the first source/drain region; a second charge-storage device coupled with the third source/drain region; a digit line coupled with the second source/drain region through an interconnect; and a switch controlling current flow along the interconnect.

8 . The integrated assembly of claim 7 wherein the interconnect comprises a length of a semiconductor material.

9 . The integrated assembly of claim 8 wherein the switch controls current flow along the length of the semiconductor material.

10 . The integrated assembly of claim 9 wherein the switch is a secondary access transistor.

11 . The integrated assembly of claim 10 wherein the secondary access transistor comprises a third gate which is electrically coupled with a multiplexer driver.

12 . The integrated assembly of claim 7 wherein the first and second primary access transistors and the first and second charge-storage devices are comprised by memory cells, and wherein the memory cells are two of many substantially identical memory cells within a DRAM array.

13 . The integrated assembly of claim 12 wherein the digit line is one of many digit lines extending along columns of the DRAM array, and wherein at least some of the digit lines extend to a common sense amplifier.

14 . The integrated assembly of claim 7 wherein the first and second charge-storage devices are first and second capacitors, respectively.

15 . An integrated assembly, comprising:
a first primary access transistor and a second primary access transistor, the first primary access transistor comprising a first gate proximate a first channel region, and the second primary access transistor comprising a second gate proximate a second channel region; the first and second primary access transistors together comprising three source/drain regions; the three source/drain regions being a first source/drain region, a second source/drain region and a third source/drain region; the first and second source/drain regions being gatedly coupled to one another through the first channel region; the second and third source/drain regions being gatedly coupled to one another through the second channel region; the first channel region extending horizontally between the first and second source/drain regions; the second channel region extending horizontally between the second and third source/drain regions; a first capacitor coupled with the first source/drain region; a second capacitor coupled with the third source/drain region; a digit line coupled with the second source/drain region through an interconnect; the interconnect comprising a vertically-extending pillar of a semiconductor material; and a secondary access transistor gating a portion of the vertically-extending pillar of the semiconductor material.

16 . The integrated assembly of claim 15 wherein the first and second primary access transistors and the first and second capacitors are comprised by memory cells, and wherein the memory cells are two of many substantially identical memory cells within a DRAM array.

17 . The integrated assembly of claim 16 wherein the digit line is one of many digit lines extending along columns of the DRAM array, and wherein at least some of the digit lines extend to a common sense amplifier.

18 . The integrated assembly of claim 15 wherein the secondary access transistor comprises a third gate; and wherein the third gate is over the first and second gates.

19 . The integrated assembly of claim 18 wherein the digit line is over the third gate.

20 . The integrated assembly of claim 18 wherein the third gate is part of a multiplexer circuit and is coupled with a multiplexer driver.

Assignees

• Micron Technology Inc

Inventors

• Derner Scott J
• Ingalls Charles L

Classifications

• G11C11/4063 Primary

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing · CPC title

• G11C2207/002

  Isolation gates, i.e. gates coupling bit lines to the sense amplifier · CPC title

• G11C11/404

  with one charge-transfer gate, e.g. MOS transistor, per cell · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title