Memory cells and memory arrays

Patent metadata

Field	Value
Publication number	US-10157926-B2
Application number	US-201715664161-A
Country	US
Kind code	B2
Filing date	Jul 31, 2017
Priority date	Aug 31, 2016
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

First claim

We claim:

1. A memory cell, comprising:
first and second transistors;
a capacitor vertically displaced relative to the first and second transistors, the capacitor having a first node electrically coupled with a source/drain region of the first transistor, having a second node electrically coupled with a source/drain region of the second transistor, and having capacitor dielectric material between the first and second nodes;
wherein the second node is shaped to include a horizontally-extending portion, and to include two pillars extending downwardly from the horizontally-extending portion; a first of the two pillars being over the source/drain region of the first transistor, and a second of the two pillars being over the source/drain region of the second transistor; the second of the two pillars being electrically coupled with the source/drain region of the second transistor; the two pillars being laterally spaced from one another by an intervening region; the second node having a bottom surface which extends downwardly along sidewalls of the two pillars, which extends along bottoms of the two pillars, and which extends along a bottom of the horizontally-extending portion across the intervening region; and
wherein the first node extends along an entirety of the bottom surface of the second node except for the bottom of the second of the two pillars.

2. The memory cell of claim 1 wherein the first and second transistors are in a common horizontal plane as one another.

3. The memory cell of claim 1 wherein:
the first transistor has a first source/drain region and a second source/drain region, and the first node is electrically coupled with the first source/drain region;
the second transistor has a third source/drain region and a fourth source/drain region, and the second node is electrically coupled with the third source/drain region; and
the second and fourth source/drain regions are electrically coupled with first and second comparative bitlines, respectively.

4. The memory cell of claim 1 wherein at least one of the first and second transistors has a gate configured to have at least one bent region, and one or more extension regions that extend along a channel region of said at least one of the first and second transistors from said at least one bent region; and wherein the gate and the one or more extension regions together form a substantially T-shaped configuration, substantially shelf-shaped configuration or substantially U-shaped configuration.

5. A memory cell comprising:
first and second transistors laterally displaced relative to one another; and
a capacitor over the first and second transistors, the capacitor having an outer node electrically coupled with a source/drain region of the first transistor, having an inner node electrically coupled with a source/drain region of the second transistor, and having capacitor dielectric material between the inner and outer nodes;
wherein the inner node is shaped to include a horizontally-extending portion, and to include two pillars extending downwardly from the horizontally-extending portion; a first of the two pillars being over the source/drain region of the first transistor, and a second of the two pillars being over the source/drain region of the second transistor; the second of the two pillars being electrically coupled and in direct contact with the source/drain region of the second transistor; the two pillars being laterally spaced from one another by an intervening region; the inner node having an outer surface which extends downwardly along sidewalls of the two pillars, which extends along bottoms of the two pillars, and which extends along a bottom of the horizontally-extending portion across the intervening region; and
wherein the outer node extends conformally along the outer surface of the inner node along the sidewalls of the two pillars, the bottom of the first pillar, and the bottom of the horizontally-extending portion across the intervening region.

6. The memory cell of claim 5 wherein the first and second transistors are in a common horizontal plane, and wherein a common wordline extends to both of the first and second transistors and comprises gates of the first and second transistors.

7. The memory cell of claim 5 wherein:
the first transistor has a first source/drain region and a second source/drain region, and the outer node is electrically coupled with the first source/drain region;
the second transistor has a third source/drain region and a fourth source/drain region, and the inner node is electrically coupled with the third source/drain region; and
the second and fourth source/drain regions are electrically coupled with first and second comparative bitlines, respectively.

8. The memory cell of claim 7 wherein the first and second comparative bitlines are in a common horizontal plane as one another.

9. The memory cell of claim 7 wherein the first and second comparative bitlines are vertically displaced relative to one another.

10. The memory cell of claim 9 wherein the first and second comparative bitlines laterally overlap one another.

11. The memory cell of claim 9 wherein the first and second comparative bitlines do not laterally overlap one another.

12. A memory array, comprising:
a pair of memory cells, each of the memory cells including:
first and second transistors laterally displaced relative to one another;
a capacitor over the first and second transistors, the capacitor having an outer node electrically coupled with a source/drain region of the first transistor, having an inner node electrically coupled with a source/drain region of the second transistor, and having capacitor dielectric material between the inner and outer nodes;
wherein the first transistor has a first source/drain region and a second source/drain region, and the outer node is electrically coupled with the first source/drain region;
wherein the second transistor has a third source/drain region and a fourth source/drain region, and the inner node is electrically coupled with the third source/drain region; and

wherein:
the second source/drain regions of both of the memory cells are electrically coupled with a first comparative bitline;
the fourth source/drain regions of both of the memory cells are electrically coupled with a second comparative bitline;
the first and second comparative bitlines are in a common horizontal plane as one another;
the memory cells are a first memory cell and a second memory cell;
an axis through the first and second comparative bitlines defines a mirror plane; and
the second memory cell is on an opposing side of the mirror plane from the first memory cell and is substantially a mirror image of the first memory cell across the mirror plane.

13. An apparatus comprising:
a semiconductor base;
an insulating film over the semiconductor base;
a memory array supported by the insulating film, and including a plurality of memory cells; each of the memory cells comprising:
a first transistor, a second transistor and a capacitor, with the capacitor having a first node coupled with a source/drain region of the first transistor and having a second node coupled with a source/drain region of the second transistor, the second node being shaped to include a horizontally-extending portion and to include two pillars extending downwardly from the horizontally-extending portion, a first of the two pillars being over the source/drain region of the first transistor and a second of the two pillars being over the source/drain region of the second transistor, the second of the two pillars being coupled with the source/drain region of the second transistor, the two p

Assignees

• Micron Technology Inc

Inventors

• Yang Gloria
• Mathew Suraj J
• Singanamalla Raghunath
• Nair Vinay
• Derner Scott J
• Shore Michael Amiel
• Keeth Brent
• Simsek-Ege Fatma Arzum
• Tran Diem Thy N

Classifications

• G11C11/403

  with charge regeneration common to a multiplicity of memory cells, i.e. external refresh · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H01L29/42376

  Electricity · mapped topic

• H01L29/1037

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic