Memory cells and memory arrays

Patent metadata

Field	Value
Publication number	US-10056386-B2
Application number	US-201715664217-A
Country	US
Kind code	B2
Filing date	Jul 31, 2017
Priority date	Aug 31, 2016
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

First claim

We claim:

1. A memory array, comprising:
two memory cells neighboring to one another along a cross-section; said two memory cells being a first memory cell and a second memory cell; the first memory cell comprising three transistors and a capacitor of a first three-transistor-one-capacitor (3T-1C) configuration; the three transistors of the first memory cell being a first transistor, a second transistor and a third transistor, and the capacitor of the first memory cell being a first capacitor; the second memory cell comprising three transistors and a capacitor of a second three-transistor-one-capacitor (3T-1C) configuration; the three transistors of the second memory cell being a fourth transistor, a fifth transistor and a sixth transistor, and the capacitor of the second memory cell being a second capacitor; the first, second, third, fourth, fifth and sixth transistors having first, second, third, fourth, fifth and sixth transistor gates, respectively;
the first and fourth transistor gates extending into a semiconductor base; the first transistor gate being coupled with a first write wordline, and the fourth transistor gate being coupled with a second write wordline;
a write bitline (WBL) being over the semiconductor base and between the first and fourth transistor gates along the cross-section;
a first capacitor being on an opposing side of the first transistor gate from the WBL along the cross-section, and a second capacitor being on an opposing side of the fourth transistor gate from the WBL along the cross-section; the first transistor gate gatedly coupling the first capacitor with the WBL, and the fourth transistor gate gatedly coupling the second capacitor with the WBL;
a first extension which couples a node of the first capacitor to the second transistor gate, and a second extension which couples a node of the second capacitor to the fifth transistor gate; the first and second extensions being spaced from one another by an intervening region; the first extension including a first elbow above the first capacitor, and the second extension comprising a second elbow above the second capacitor; the first elbow being substantially a mirror image of the second elbow along a plane passing vertically through a center of the WBL;
a rail of conductive material coupled with common plate (CP) voltage; the rail being beneath the second and fifth transistor gates;
a first semiconductor pillar extending from a top of the rail to a bottom of a read bitline (RBL), with the second transistor gate being adjacent the first semiconductor pillar; a second semiconductor pillar extending from a top of the rail to the bottom of the RBL, with the fifth transistor gate being adjacent the second semiconductor pillar;
the third transistor gate being above the second transistor gate and being adjacent the first semiconductor pillar; and the sixth transistor gate being above the fifth transistor gate and being adjacent the second semiconductor pillar; the third transistor gate being coupled with a first read wordline, and the sixth transistor gate being coupled with a second read wordline;
the third transistor gate gatedly coupling the RBL with a region of the first semiconductor pillar between the second and third transistor gates, and the second transistor gate gatedly coupling the CP voltage of the rail with the region of the first semiconductor pillar between the second and third transistor gates;
the sixth transistor gate gatedly coupling the RBL with a region of the second semiconductor pillar between the fifth and sixth transistor gates, and the fifth transistor gate gatedly coupling the CP voltage of the rail with the region of the second semiconductor pillar between the fifth and sixth transistor gates.

2. The memory array of claim 1 wherein first and second capacitors extend into the semiconductor base.

3. The memory array of claim 1 wherein first and second capacitors extend downwardly to below the first and fourth transistor gates.

4. The memory array of claim 1 wherein the first and second capacitors are over the semiconductor base.

5. The memory array of claim 1 wherein the rail is directly against outer nodes of the first and second capacitors.

6. The memory array of claim 1 wherein the rail is not directly against outer nodes of the first and second capacitors.

Assignees

• Micron Technology Inc

Inventors

• Mathew Suraj J
• Brown Kris K
• Singanamalla Raghunath
• Nair Vinay
• Ahmed Fawad
• Simsek-Ege Fatma Arzum
• Tran Diem Thy N

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L29/1037

  Electricity · mapped topic

• H01L27/10841

  Electricity · mapped topic

• H01L27/0688

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic