Methods and apparatus for high voltage integrated circuit capacitors

Patent metadata

Field	Value
Publication number	US-9741787-B2
Application number	US-201615348698-A
Country	US
Kind code	B2
Filing date	Nov 10, 2016
Priority date	Nov 6, 2014
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

High voltage integrated circuit capacitors are disclosed. In an example arrangement. A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

First claim

What is claimed is:

1. A method, comprising:
providing a semiconductor substrate;
forming a capacitor bottom plate of conductive material overlying the semiconductor substrate;
forming a capacitor dielectric layer overlying at least a portion of the capacitor bottom plate, the capacitor dielectric layer having a thickness of at least 6 ums;
forming a gradient photoresist layer over the capacitor dielectric layer defining a first region in the capacitor dielectric having a first thickness and a defining a second region having a second thickness that is less than the first thickness;
etching the capacitor dielectric layer to form the first region, the second region, and forming a transition region between the first region and the second region, the transition region having a sloped top surface with a slope from a horizontal plane greater than about 5 degrees; and
forming a top plate conductor overlying at least a portion of the first region of the capacitor dielectric layer.

2. The method of claim 1 , wherein forming the capacitor dielectric layer comprises forming in a single deposition step a monolithic capacitor dielectric layer that is one selected from the group consisting essentially of an oxide layer and an oxynitride layer.

3. The method of claim 2 , wherein forming in a single deposition step further comprises performing a TEOS deposition.

4. The method of claim 1 , wherein forming the capacitor dielectric layer further comprises forming the capacitor dielectric layer in a series of dielectric deposition steps to form multiple layers of dielectric.

5. The method of claim 4 wherein forming the multiple layers of dielectric comprises forming a series of layers each one selected from the group consisting essentially of an oxide layer and an oxynitride layer.

6. The method of claim 1 , wherein forming the capacitor dielectric layer further comprises a series of dielectric deposition steps to form alternating compressive layers and tensile layers of dielectric.

7. The method of claim 1 , and further comprising forming at least one insulating layer between the bottom plate and the capacitor dielectric layer, the insulating layer having a thickness of at least 3 ums.

8. The method of claim 7 wherein a sum of the thicknesses of the capacitor dielectric layer and the thickness of the at least one insulating layer is greater than about 9 ms.

9. The method of claim 8 , wherein an area of the capacitor dielectric layer is less than 25% of a total area of the semiconductor substrate.

10. The method of claim 1 , and further comprising forming an upper layer over the capacitor dielectric layer that lies between the top of the capacitor dielectric layer and the top plate conductor, the upper layer comprising silicon nitride and silicon oxynitride.

11. The method of claim 10 , and further comprising forming openings in the upper layer by photolithographic pattern and etch processes.

Assignees

• Texas Instruments Inc

Inventors

• West Jeffrey Alan
• Bonifield Thomas D
• Williams Byron Lovell

Classifications

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/547

  Dispositions of multiple bond wires · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title