Fabrication method and structure of semiconductor non-volatile memory device

Patent metadata

Field	Value
Publication number	US-2016197091-A1
Application number	US-201615067444-A
Country	US
Kind code	A1
Filing date	Mar 11, 2016
Priority date	Dec 4, 2002
Publication date	Jul 7, 2016
Grant date	—

Abstract

A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a semiconductor substrate having a main surface, the main surface including a memory cell region and a peripheral circuit region in a plan view; a first transistor formed in the main surface of the semiconductor substrate in the memory cell region; and a second transistor formed in the main surface of the semiconductor substrate in the peripheral circuit region; wherein the first transistor comprises: a first gate electrode having a first polycrystalline film and a second polycrystalline film stacked on the first polycrystalline film over the main surface of the semiconductor substrate via a first gate insulating film; a charge accumulating region comprised of a second gate electrode formed on the main surface of the semiconductor substrate via a second gate insulating film, the second gate electrode being disposed at a sidewall surface of the first gate electrode; and first insulating sidewall spacers comprising a first insulating film formed on the side surfaces of the first gate electrode and the second gate electrode, wherein second transistor has a third gate electrode having a third polycrystalline film and a fourth polycrystalline film stacked on the third polycrystalline film over the main surface of the semiconductor substrate via an insulating film part formed of the same layer as that of the first gate insulating film, wherein second insulating sidewall spacers comprise a second insulator film formed on the side surfaces of the third gate electrode, wherein the first polycrystalline film and third polycrystalline film are formed of the same layer, wherein the second polycrystalline film and fourth polycrystalline film are formed of the same layer, wherein a thickness of each of the first and third polycrystalline films is smaller than a thickness of each of the second and fourth polycrystalline films, and wherein the first insulating film and the second insulating film comprise an insulating film of the same layer.

2 . The semiconductor device according to claim 1 ,
wherein the charge accumulating region comprises a silicon nitride film.

3 . The semiconductor device according to claim 1 ,
wherein each of first and third gate electrodes comprises an impurity doped polycrystalline film.

Assignees

• Renesas Electronics Corp

Inventors

• Hisamoto Digh
• Kimura Shinichiro
• Yasui Kan
• Matsuzaki Nozomu

Classifications

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D30/696

  having at least one additional gate, e.g. program gate, erase gate or select gate · CPC title

• H10D30/69 Primary

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H01L27/11573

  Electricity · mapped topic

• H01L27/11568 Primary

  Electricity · mapped topic