Methods for forming etch stop layers, semiconductor devices having the same, and methods for fabricating semiconductor devices

Patent metadata

Field	Value
Publication number	US-9437483-B2
Application number	US-201414218091-A
Country	US
Kind code	B2
Filing date	Mar 18, 2014
Priority date	Nov 17, 2010
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion.

First claim

What is claimed is:

1. A method of fabricating a memory device comprising:
providing a plurality of insulation layers on a substrate extending in a horizontal direction;
providing a plurality of conductive layers, each of at least two of the conductive layers between a neighboring lower insulation layer and a neighboring upper insulation layer;
providing a plurality of vertical channels of semiconductor material extending in a vertical direction through the plurality of insulation layers and the plurality of conductive layers;
providing a gate insulating layer between each of the at least two of the conductive layers and the vertical channels that insulates the at least two of the conductive layers from the vertical channels;
etching the at least two of the conductive layers to form at least two conductive patterns and conductive contact regions of the at least two of the conductive patterns, the conductive contact regions of the at least two of the conductive patterns being in a stepped configuration so that a contact region of a neighboring lower conductive pattern extends in the horizontal direction beyond a contact region of a neighboring upper conductive pattern; and
providing an etch stop layer on the conductive contact regions, the etch stop layer having a first portion on a first one of the plurality of conductive patterns and having a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion.

2. The method of claim 1 wherein etching each conductive layer comprises:
providing a first mask on the plurality of conductive layers and the plurality of insulation layers;
a first etching step comprising etching a first one of a plurality of the conductive layers using the first mask as an etch mask;
a first trimming step comprising trimming the first mask to expose an upper portion of the first one of the plurality of the conductive layers; and
a second etching step comprising etching the first one of the plurality of the conductive layers and a second one of the plurality of the conductive layers using the trimmed first mask as an etch mask.

3. The method of claim 2 further comprising repeating the first trimming step and the second etching step to thereby etch further conductive layers of the plurality of conductive layers lying below the first one and the second one of the conductive layers.

4. The method of claim 2 further comprising:
providing a first etch stop layer on a first set of the conductive layers etched by the trimming and second etching steps;
providing a second mask on the first etch stop layer;
a third etching step comprising etching a third one of a plurality of the conductive layers using the second mask as an etch mask;
a second trimming step comprising trimming the second mask to expose an upper portion of the third one of the plurality of the conductive layers; and
a fourth etching step comprising etching the third one of the plurality of the conductive layers and a fourth one of the plurality of the conductive layers using the trimmed first mask as an etch mask.

5. The method of claim 4 further comprising repeating the second trimming step and the fourth etching step to thereby etch further conductive layers of the plurality of conductive layers lying below the third one and the fourth one of the plurality of conductive layers.

6. The method of claim 5 further comprising: providing a second etch stop layer on the first etch stop layer and on a second set of the conductive layers etched by the second trimming and fourth etching steps.

7. The method of claim 6 :
wherein portions of the first etch stop layer and second etch stop layer remain on the conductive contact regions of the first set of the conductive layers to provide the first portion of the etch stop layer; and
wherein portions of the second etch stop layer remain on the conductive contact regions of the second set of the conductive layers to provide the second portion of the etch stop layer.

8. The method of claim 1 wherein etching each conductive layer comprises:
providing a first mask on the plurality of conductive layers and the plurality of insulation layers;
a first etching step comprising etching a first one of the plurality of the conductive layers using the first mask as an etch mask;
a first applying step comprising applying a first sidewall to the first mask and the first one of the plurality of conductive layers etched by the first etching step to form a second mask; and
a second etching step comprising etching a second one of the plurality of the conductive layers lying below the first one of the plurality of conductive layers using the second mask as an etch mask.

9. The method of claim 8 further comprising repeatedly applying a sidewall to a most recent mask and to a most recently etched one of the plurality of conductive layers and etching an underlying one of the plurality of conductive layers using the sidewall and the most recent mask as an etch mask.

10. The method of claim 8 further comprising:
providing a first etch stop layer on a first set of the conductive layers etched by the first applying and second etching steps;
providing a second mask on the first etch stop layer;
a third etching step comprising etching a third one of the plurality of the conductive layers using the second mask as an etch mask;
a second applying step comprising applying a sidewall to the second mask and the third one of the plurality of conductive layers etched by the third etching step to form a third mask; and
a fourth etching step comprising etching a fourth one of the plurality of the conductive layers lying below the third one of the plurality of conductive layers using the third mask as an etch mask.

11. The method of claim 10 further comprising repeatedly applying a sidewall to a most recent second mask and to a most recently etched one of the plurality of conductive layers and etching an underlying one of the plurality of conductive layers using the sidewall and the most recent second mask as an etch mask.

12. The method of claim 11 further comprising: providing a second etch stop layer on the first etch stop layer and on a second set of the conductive layers etched by the second applying and fourth etching steps.

13. The method of claim 12 :
wherein portions of the first etch stop layer and second etch stop layer remain on the conductive contact regions of the first set of the conductive layers to provide the first portion of the etch stop layer; and
wherein portions of the second etch stop layer remain on the conductive contact regions of the second set of the conductive layers to provide the second portion of the etch stop layer.

14. The method of claim 1 wherein the first one of the plurality of conductive patterns is at a layer above a layer of the second one of the plurality of conductive patterns.

15. The method of claim 1 wherein providing the etch stop layer comprises providing the first portion of the etch stop layer to include multiple layers and providing the second portion of the etch stop layer to include one or more layers, the number of layers of the second portion being fewer in number than the number of layers of the first portion.

16. The method of claim 1 further comprising:
providing an upper insulator on the conductive contact regions of the conductive patterns; and
providing a plurality of vertical interconnects, each vertical interconnect contacting one of the conductive contact regions of the conductive patterns through the u

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jaegoo
• Park Youngwoo

Classifications

• H10W20/075 Primary

  of multilayered thin functional dielectric layers · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H01L27/11519

  Electricity · mapped topic

• H01L27/11578

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic