Semiconductor memory devices including asymmetric word line pads

Patent metadata

Field	Value
Publication number	US-9911750-B2
Application number	US-201614996821-A
Country	US
Kind code	B2
Filing date	Jan 15, 2016
Priority date	Jun 24, 2010
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

Semiconductor memory devices may include a semiconductor substrate, a first stack disposed on the semiconductor substrate and a second stack disposed on the first stack. The first stack may include a plurality of first word lines with a plurality of first line pads stacked in a stair form, and the second stack may include a plurality of second word lines with a plurality of second line pads stacked in a stair form. The second stack may be shifted on the first stack such that sides of the plurality of first word line pads are exposed.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a first stack including a plurality of first word lines having substantially identical widths in a first direction and different lengths in a second direction crossing the first direction, the plurality of first word lines including a plurality of first contact regions at edges of the plurality of first word lines;
a second stack on the first stack, the second stack including a plurality of second word lines having substantially identical widths in the first direction and different lengths in the second direction, the second word lines including a plurality of second contact regions at edges of the plurality of second word lines;
a third stack on the second stack, the third stack including a plurality of third word lines having substantially identical widths in the first direction and different lengths in the second direction, the plurality of third word lines including a plurality of third contact regions at edges of the plurality of third word lines;
a fourth stack on the third stack the fourth stack including a plurality of fourth word lines having substantially identical widths in the first direction and different lengths in the second direction, the plurality of fourth word lines including a plurality of fourth contact regions at edges of the plurality of fourth word lines;
at least one bit line on the fourth stack that extends along the first direction; and
a first contact group including a plurality of first pad contacts in contact with the plurality of first contact regions, the plurality of first pad contacts aligned along the second direction;
a second contact group including a plurality of second pad contacts in contact with the plurality of second contact regions, the plurality of second pad contacts aligned along the second direction,
a third contact group including a plurality of third pad contacts in contact with the plurality of third contact regions, the plurality of third pad contacts aligned along the second direction,
a fourth contact group including a plurality of fourth pad contacts in contact with the plurality of fourth contact regions, the plurality of fourth pad contacts aligned along the second direction,
one of the first contact group, the second contact group, the third contact group, and the fourth contact group being shifted along the first direction compared to another of the first contact group, the second contact group, the third contact group, and the fourth contact group, wherein
the first contact regions include a plurality of first word lines pads stacked stepwise along a third direction crossing the first and second directions,
the plurality of first word line pads include a second side opposite a first side,
the second contact regions include a plurality of second word lines pads stacked stepwise along the third direction,
the plurality of second word line pads include a third side overlapping the first side and a fourth side overlapping the second side,
the third contact regions include a plurality of third word lines pads stacked stepwise along the third direction,
the plurality of third word line pads include a fifth side overlapping the third side and a sixth side overlapping the fourth side,
the fourth contact regions include a plurality of fourth word lines pads stacked stepwise along the third direction, and
the plurality of fourth word line pads include a seventh side overlapping the fifth side and an eighth side overlapping the sixth side.

2. The semiconductor memory device of claim 1 , wherein
the plurality of first pad contacts are in contact with the plurality of first word line pads on the first side,
the plurality of second pad contacts are in contact with the plurality of second word line pads on the fourth side,
the plurality of third pad contacts are in contact with the plurality of third word line pads on the fifth side, and
the plurality of fourth pad contacts are in contact with the plurality of fourth word line pads on the eighth side.

3. The semiconductor memory device of claim 2 , wherein
the first and third contact groups are at one side of the at least one bit line, and
the second and fourth contact groups are at the other side of the at least one bit line.

4. The semiconductor memory device of claim 3 , wherein
the first contact group overlaps the third contact group along the first direction, and
the second contact group overlaps the fourth contact group along the first direction.

Assignees

• Lee Jaegoo
• Samsung Electronics Co Ltd

Inventors

• Lee Jaegoo

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L27/11551

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic