Method of fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-10847362-B2
Application number	US-201816155976-A
Country	US
Kind code	B2
Filing date	Oct 10, 2018
Priority date	Apr 2, 2018
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

A method of fabricating a semiconductor device, the method including forming semiconductor patterns on a substrate such that the semiconductor patterns are vertically spaced apart from each other; and forming a metal work function pattern to fill a space between the semiconductor patterns, wherein forming the metal work function pattern includes performing an atomic layer deposition (ALD) process to form an alloy layer, and the ALD process includes providing a first precursor containing an organoaluminum compound on the substrate, and providing a second precursor containing a vanadium-halogen compound on the substrate.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming semiconductor patterns on a substrate such that the semiconductor patterns are vertically spaced apart from each other; and
forming a metal work function pattern to fill a space between the semiconductor patterns,
wherein:
forming the metal work function pattern includes performing an atomic layer deposition (ALD) process to form an alloy layer, and
the ALD process includes:
providing a first precursor containing an organoaluminum compound on the substrate, and
providing a second precursor containing a vanadium-halogen compound on the substrate.

2. The method as claimed in claim 1 , wherein:
the organoaluminum compound is represented by the following Chemical Formula 1:

in Chemical Formula 1, R 1 to R 3 are each independently a hydrogen atom, a C 1 -C 10 alkyl group, a C 3 -C 10 alkenyl group, or a C 3 -C 10 alkynyl group, provided that at least one of R 1 to R 3 is a C 1 -C 10 alkyl group, a C 3 -C 10 alkenyl group, or a C 3 -C 10 alkynyl group.

3. The method as claimed in claim 1 , wherein the vanadium-halogen compound includes VCl 4 , VCl 5 , VF 4 , VF 5 , VBr 4 , or VBr 5 .

4. The method as claimed in claim 1 , further comprising forming an electrode pattern on the metal work function pattern such that the electrode pattern is formed of a low resistance metal material that has a resistance that is lower than a resistance of the metal work function pattern.

5. The method as claimed in claim 4 , wherein:
the metal work function pattern is formed to completely fill the space between the semiconductor patterns, and
the electrode pattern is absent in the space between the semiconductor patterns.

6. The method as claimed in claim 1 , wherein:
forming the metal work function pattern further includes forming a metal nitride layer prior to forming the alloy layer, and
the metal nitride layer has a work function that is higher than a work function of the alloy layer.

7. The method as claimed in claim 1 , wherein providing the second precursor on the substrate includes reacting the second precursor with a hydrocarbon in the first precursor to form a C—V bond.

8. The method as claimed in claim 1 , wherein the alloy layer has a chemical structure of V x Al y C z , in which x ranges from 20 to 40, y ranges from 5 to 30, and z ranges from 30 to 55.

9. The method as claimed in claim 1 , wherein forming the semiconductor patterns includes:
alternately and repeatedly stacking sacrificial layers and semiconductor layers on the substrate;
patterning the sacrificial layers and the semiconductor layers to form a preliminary active pattern including sacrificial patterns and semiconductor patterns; and
selectively removing the sacrificial patterns.

10. The method as claimed in claim 9 , wherein selectively removing the sacrificial patterns includes:
forming sacrificial gate pattern to cross the preliminary active pattern;
forming an interlayered insulating layer on the substrate; and
selectively removing the sacrificial gate pattern to form a trench in the interlayered insulating layer such that the trench exposes the sacrificial patterns and the semiconductor patterns.

11. The method as claimed in claim 10 , further comprising:
etching portions of the preliminary active pattern at both sides of the sacrificial gate pattern; and
performing a selective epitaxial process to form a pair of source/drain patterns at both sides of the sacrificial gate pattern.

12. A method of fabricating a semiconductor device, the method comprising:
forming a gate electrode on a substrate such that the gate electrode includes an alloy layer including vanadium and aluminum,
wherein forming the gate electrode including the alloy layer includes:
providing a first precursor on the substrate;
providing a second precursor containing a vanadium-halogen compound on the substrate; and
forming a metal nitride layer prior to the forming of the alloy layer such that the metal nitride layer has a work function that is higher than a work function of the alloy layer,
wherein the first precursor includes a compound represented by the following Chemical Formula 1:

and
wherein, in Chemical Formula 1, R 1 to R 3 are each independently a hydrogen atom, a C 1 -C 10 alkyl group, a C 3 -C 10 alkenyl group, or a C 3 -C 10 alkynyl group, provided that at least one of R 1 to R 3 is a C 1 -C 10 alkyl group, a C 3 -C 10 alkenyl group, or a C 3 -C 10 alkynyl group.

13. The method as claimed in claim 12 , wherein the vanadium-halogen compound includes VCl 4 , VCl 5 , VF 4 , VF 5 , VBr 4 , or VBr 5 .

14. The method as claimed in claim 12 , wherein forming the gate electrode further includes forming an electrode pattern on the alloy layer such that the electrode pattern is formed of a low resistance metal material having a resistance that is lower than a resistance of the alloy layer.

15. The method as claimed in claim 12 , wherein the alloy layer has a chemical structure of V x Al y C z , in which x ranges from 20 to 40, y ranges from 5 to 30, and z ranges from 30 to 55.

16. A method of fabricating a semiconductor device, the method comprising:
forming semiconductor patterns on a substrate such that the semiconductor patterns are vertically spaced apart from each other; and
performing an atomic layer deposition (ALD) process to form a VAlC metal work function pattern to fill a space between the semiconductor patterns,
wherein the ALD process includes a plurality of process cycles, each process cycle including:
providing a first precursor on the substrate, and
providing a second precursor containing VCl 4 on the substrate,
wherein the first precursor includes a compound represented by the following Chemical Formula 1:

and
wherein, in Chemical Formula 1, R 1 to R 3 are each independently a hydrogen atom, a C 1 -C 10 alkyl group, a C 3 -C 10 alkenyl group, or a C 3 -C 10 alkynyl group, provided that at least one of R 1 to R 3 is a C 1 -C 10 alkyl group, a C 3 -C 10 alkenyl group, or a C 3 -C 10 alkynyl group.

17. The method as claimed in claim 16 , wherein providing the second precursor on the substrate includes reacting the second precursor with a hydrocarbon in the first precursor to form a C—V bond.

18. The method as claimed in claim 16 , wherein:
the VCl 4 is provided from a container,
the VCl 4 in the container is in a liquid state,
providing the second precursor includes:
heating and evaporating the VCl 4 in the container; and
feeding the evaporated VCl 4 into a process chamber, in which the substrate is provided, using a carrier gas.

19. The method as claimed in claim 16 , wherein providing the first precursor includes controlling a feeding time of the first precursor such that a work function and resistivity of the VAlC layer is adjusted to predetermined levels.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Gyu-Hee
• Park Yangsun
• Lim Jaesoon
• Cho Younjoung

Classifications

• H10P50/264

  by chemical means · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10P14/6339 Primary

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title