Stratified gate dielectric stack for gate dielectric leakage reduction

Patent metadata

Field	Value
Publication number	US-9627214-B2
Application number	US-201615200141-A
Country	US
Kind code	B2
Filing date	Jul 1, 2016
Priority date	Apr 18, 2012
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a dielectric material having a different band gap than the first high-k dielectric material, and a second high-k gate dielectric comprising a second high-k dielectric material. The band-gap-disrupting dielectric includes at least one contiguous atomic layer of the dielectric material. Thus, the stratified gate dielectric stack includes a first atomic interface between the first high-k gate dielectric and the band-gap-disrupting dielectric, and a second atomic interface between the second high-k gate dielectric and the band-gap-disrupting dielectric that is spaced from the first atomic interface by at least one continuous atomic layer of the dielectric material of the band-gap-disrupting dielectric. The insertion of the band-gap disrupting dielectric results in lower gate leakage without resulting in any substantial changes in the threshold voltage characteristics and effective oxide thickness.

First claim

What is claimed is:

1. A method of forming a semiconductor structure including a field effect transistor (FET), said method comprising:
forming a high dielectric constant (high-k) gate dielectric material stack on a semiconductor substrate and comprising a lower high-k dielectric material and an upper high-k dielectric material in direct contact with said lower high-k dielectric material, wherein said lower high-k dielectric has a horizontal portion location on said semiconductor substrate and vertical portions extending upward from said horizontal portion;
forming a band-gap-disrupting dielectric layer comprising a dielectric material having a different band gap than said upper high-k dielectric material and on a topmost surface of said high-k gate dielectric material stack;
forming a second high-k gate dielectric layer comprising a second high-k dielectric material having a different band gap than said band-gap-disrupting dielectric of said band-gap-disrupting dielectric layer; and
patterning a stack of said high-k gate dielectric material stack, said band-gap-disrupting dielectric layer, and said second high-k gate dielectric layer to form a stratified gate dielectric stack of a remaining portion of said high-k dielectric material stack, a band-gap-disrupting dielectric, and a second high-k gate dielectric, wherein a first atomic interface between said band-gap-disrupting dielectric and said remaining portion of said high-k gate dielectric material stack is spaced from a second atomic interface between said band-gap-disrupting dielectric and said second high-k gate dielectric by at least one continuous atomic layer of said dielectric material of said band-gap-disrupting dielectric within said stratified gate dielectric stack.

2. The method of claim 1 , wherein said forming of said stratified gate dielectric stack comprises preserving said high-k gate dielectric material stack to be substantially free of said dielectric material of said band-gap-disrupting dielectric until, and during, said patterning of said stack.

3. The method of claim 2 , wherein said forming of said stratified gate dielectric stack further comprises preserving said second high-k dielectric material to be substantially free of said dielectric material of said band-gap-disrupting dielectric until, and during, said patterning of said stack.

4. The method of claim 3 , wherein said forming of said stratified gate dielectric stack further comprises preserving said dielectric material of said band-gap-disrupting dielectric to be substantially free of said lower high-k dielectric material, said upper high-k dielectric material and said second high-k dielectric material until, and during, said patterning of said stack.

5. The method of claim 1 , wherein said forming of said second high-k gate dielectric layer comprises depositing a same material as said upper high-k dielectric material as said second high-k dielectric material.

6. The method of claim 1 , wherein said forming of said second high-k gate dielectric layer comprises depositing a material having a different composition from a composition of said upper high-k dielectric material.

7. The method of claim 1 , further comprising forming a gate cavity laterally surrounded by a planarization dielectric layer on said semiconductor substrate, wherein each of said high-k gate dielectric material stack, said band-gap-disrupting dielectric layer, and said second high-k gate dielectric layer are sequentially deposited within said gate cavity.

8. The method of claim 7 , further comprising:
forming a disposable gate structure on said semiconductor substrate prior to forming said planarization dielectric layer; and
planarizing said planarization dielectric layer, wherein a topmost surface of said disposable gate structure is coplanar with a top surface of said planarization dielectric layer after said planarizing, and said gate cavity is formed by removing said disposable gate structure after said planarizing of said planarization dielectric layer.

9. The method of claim 7 , wherein said patterning of said stack of said high-k gate dielectric material stack, said band-gap-disrupting dielectric layer, and said second high-k gate dielectric layer comprises removing portions of said high-k gate dielectric material stack, said band-gap-disrupting dielectric layer, and said second high-k gate dielectric layer from above a top surface of said planarization dielectric layer.

10. The method of claim 7 , further comprising:
forming a work function material layer on said second high-k dielectric layer and within said gate cavity;
forming a conductive material layer on said work function material layer and within said gate cavity; and
removing portions of said work function material layer and said conductive material layer from above a planarized surface of said planarization dielectric layer.

11. The method of claim 7 , further comprising forming a gate spacer on sidewalls of said disposable gate structure, wherein said high-k gate dielectric material stack is deposited directly on inner sidewalls of said gate spacer.

12. The method of claim 1 , further comprising maintaining said stratified gate dielectric stack under a temperature that induces detectable interdiffusion of materials across said first atomic interface or said second atomic interface at least until at least said field effect transistor is incorporated into a functional semiconductor chip.

13. The method of claim 1 , wherein said band-gap-disrupting dielectric layer is formed by a substantially conformal deposition method that forms said band-gap-disrupting dielectric layer as a single contiguous layer.

14. The method of claim 1 , wherein said band-gap-disrupting dielectric layer is formed by a non-conformal deposition method that forms said band-gap-disrupting dielectric layer as at least two disjoined portions including an upper portion overlying a planarization dielectric layer and a lower portion located underneath a top surface of said planarization dielectric layer.

15. The method of claim 14 , wherein a vertical portion of said second high-k gate dielectric layer is deposited directly on a sidewall of said high-k gate dielectric material stack.

16. The method of claim 1 , further comprising forming a gate spacer directly on sidewalls of said vertical portions of said lower high-k dielectric material in said high-k gate dielectric material stack.

17. The method of claim 1 , wherein said semiconductor substrate comprises a semiconductor fin.

18. The method of claim 1 , further comprising forming an interface dielectric located over a portion of said semiconductor substrate prior to said forming said high-k gate dielectric material stack, wherein said interface dielectric is located beneath said horizontal portion of said lower high-k dielectric material, and is formed by converting a surface portion of a semiconductor material of said semiconductor substrate into a dielectric material comprising said semiconductor material and at least one of oxygen and nitrogen.

19. The method of claim 1 , wherein said lower high-k dielectric material has a different composition different from a composition of said upper high-k dielectric material.

Assignees

• IBM

Inventors

• Jagannathan Hemanth
• Jamison Paul C

Classifications

• H10D64/01346 Primary

  in a gaseous ambient using an oxygen or a water vapour, e.g. oxidation through a layer (H10D64/01344 takes precedence) · CPC title

• H10D64/01344

  in a nitrogen-containing ambient, e.g. N2O oxidation · CPC title

• H10D64/01332

  Making the insulator · CPC title

• H10P14/40 Primary

  of conductive or resistive materials · CPC title

• H01L29/7833

  Electricity · mapped topic