Active device substrate and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10840380-B2
Application number	US-201916388887-A
Country	US
Kind code	B2
Filing date	Apr 19, 2019
Priority date	Apr 19, 2018
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

An active device substrate includes a substrate, a first active device, and a second active device. The first active device includes a first gate, a crystallized metal oxide layer, a first insulation layer, a first source, and a first drain. The crystallized metal oxide layer is located on the first gate. The first insulation layer is sandwiched between the crystallized metal oxide layer and the first gate. An area from the top surface of the crystallized metal oxide layer to the bottom surface of the crystallized metal oxide layer is observed via a selected area diffraction mode of a transmission electron microscope, and a diffraction pattern of a crystallized phase can be observed. The second active device includes a second gate, a silicon semiconductor layer, a second source, and a second drain. A manufacturing method of an active device substrate is further provided.

First claim

What is claimed is:

1. A manufacturing method of an active device substrate, comprising:
forming a first gate on a substrate;
forming a first insulation layer on the first gate;
forming a non-crystallized metal oxide layer on the first gate;
forming a second insulation layer on the non-crystallized metal oxide layer;
forming a non-crystallized silicon layer on the second insulation layer, and the non-crystallized metal oxide layer is located between the non-crystallized silicon layer and the first gate;
performing a rapid thermal annealing process to transform the non-crystallized metal oxide layer into a crystallized metal oxide layer; and
forming a first source and a first drain electrically connected to the crystallized metal oxide layer.

2. The manufacturing method of the active device substrate of claim 1 , wherein the rapid thermal annealing process has a maximum temperature of 400 degrees to 700 degrees and a duration of 30 seconds to 6 minutes.

3. The manufacturing method of the active device substrate of claim 1 , further comprising:
forming a second gate on the substrate;
forming a silicon semiconductor layer, wherein the silicon semiconductor layer at least covers a portion of the second gate; and
forming a second source and a second drain electrically connected to the silicon semiconductor layer.

4. The manufacturing method of the active device substrate of claim 3 , wherein a method of forming the silicon semiconductor layer comprises:
removing a portion of the non-crystallized silicon layer, wherein a remaining non-crystallized silicon layer comprises the silicon semiconductor layer.

5. The manufacturing method of the active device substrate of claim 3 , wherein a method of forming the silicon semiconductor layer comprises:
transforming the non-crystallized silicon layer into a polycrystalline silicon layer via a laser;
removing a portion of the polycrystalline silicon layer, wherein a remaining polycrystalline silicon layer comprises the silicon semiconductor layer.

6. The manufacturing method of the active device substrate of claim 3 , wherein the first gate and the second gate are formed together.

7. The manufacturing method of the active device substrate of claim 3 , wherein the first insulation layer and the second insulation layer are sandwiched between the silicon semiconductor layer and the second gate.

8. The manufacturing method of the active device substrate of claim 1 , wherein a material of the first insulation layer and the second insulation layer comprises silicon oxide.

9. The manufacturing method of the active device substrate of claim 1 , wherein a thickness of the first insulation layer is 50 nm to 300 nm, and a thickness of the second insulation layer is 50 nm to 300 nm.

10. The manufacturing method of the active device substrate of claim 1 , wherein a material of the first gate comprises titanium or a combination of titanium and aluminum.

Assignees

• Au Optronics Corp

Inventors

• Ye jia-hong

Classifications

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10P14/3808

  using laser beams · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title