Nanowire structures having wrap-around contacts

Patent metadata

Field	Value
Publication number	US-10483385-B2
Application number	US-201113995914-A
Country	US
Kind code	B2
Filing date	Dec 23, 2011
Priority date	Dec 23, 2011
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.

First claim

What is claimed is:

1. A nanowire semiconductor device, comprising:
a nanowire disposed above a substrate;
a channel region disposed in the nanowire, the channel region having a length and a perimeter orthogonal to the length, wherein the perimeter of the channel region is a smallest perimeter of the nanowire;
a gate electrode stack surrounding the entire perimeter of the channel region;
a pair of source and drain regions disposed in the nanowire, on either side of the channel region, each of the source and drain regions having a perimeter orthogonal to the length of the channel region, wherein the perimeters of the source and drain regions are approximately the same, and are greater than the perimeter of the channel region at locations immediately adjacent the channel region, and wherein the smallest perimeter of the nanowire is at the locations where the source and drain regions are immediately adjacent the channel region;
a pair of conductive contacts, a first of the pair of conductive contacts completely surrounding and in contact with the entire perimeter of the source region, and a second of the pair of conductive contacts completely surrounding and in contact with the entire perimeter of the drain region, wherein the pair of conductive contacts has an uppermost surface co-planar with an uppermost surface of the gate electrode stack;
a pair of spacers disposed between the gate electrode stack and the pair of conductive contacts; and
an intervening semiconductor material below and in contact with the nanowire but not along sidewalls of the nanowire at a location beneath the pair of spacers.

2. The nanowire semiconductor device of claim 1 , wherein the channel region has a width and a height, the width approximately the same as the height, and wherein each of the source and drain regions has a width and a height, the width approximately the same as the height.

3. The nanowire semiconductor device of claim 1 , wherein the nanowire consists essentially of silicon, and the entire perimeter of each of the source and drain regions is an exposed <111> silicon surface.

4. The nanowire semiconductor device of claim 1 , further comprising:
a doping layer disposed on and completely surrounding the perimeter of each of the source and drain regions, between the source and drain regions and the pair of conductive contacts.

5. The nanowire semiconductor device of claim 1 , wherein the gate electrode stack comprises a metal gate and a high-K gate dielectric, and the nanowire comprises silicon, germanium, or a combination thereof.

6. The nanowire semiconductor device of claim 1 , wherein the channel region has a width and a height, the width substantially greater than the height, and wherein each of the source and drain regions has a width and a height, the width substantially greater than the height.

7. The nanowire semiconductor device of claim 6 , wherein the nanowire consists essentially of silicon, the perimeter along the width of each of the source and drain regions comprises exposed <110> silicon surfaces, and the perimeter along the height of each of the source and drain regions comprises exposed <100> silicon surfaces.

8. The nanowire semiconductor device of claim 1 , wherein the channel region has a width and a height, the width substantially less than the height, and wherein each of the source and drain regions has a width and a height, the width substantially less than the height.

9. The nanowire semiconductor device of claim 8 , wherein the nanowire consists essentially of silicon, the perimeter along the width of each of the source and drain regions comprises exposed <100> silicon surfaces, and the perimeter along the height of each of the source and drain regions comprises exposed <110> silicon surfaces.

10. A semiconductor device, comprising:
a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising:
a discrete channel region disposed in the nanowire, the channel region having a length and a perimeter orthogonal to the length, wherein the perimeter of the channel region is a smallest perimeter of the nanowire;
a pair of discrete source and drain regions disposed in the nanowire, on either side of the channel region, each of the source and drain regions having a perimeter orthogonal to the length of the channel region, wherein the perimeters of the source and drain regions are approximately the same, and are greater than the perimeter of the channel region at locations immediately adjacent the channel region, and wherein the smallest perimeter of the nanowire is at the locations where the source and drain regions are immediately adjacent the channel region;

a gate electrode stack surrounding and in contact with the entire perimeter of each of the channel regions;
a pair of conductive contacts, a first of the pair of conductive contacts completely surrounding the perimeter of each of the source regions, and a second of the pair of conductive contacts completely surrounding and in contact with the entire perimeter of each of the drain regions, wherein the pair of conductive contacts has an uppermost surface co-planar with an uppermost surface of the gate electrode stack;
a pair of spacers disposed between the gate electrode stack and the pair of conductive contacts; and
an intervening semiconductor material between and in contact with the plurality of vertically stacked nanowires but not along sidewalls of the nanowires at a location beneath the pair of spacers.

11. The semiconductor device of claim 10 , wherein each of the channel regions has a width and a height, the width approximately the same as the height, and wherein each of the source and drain regions has a width and a height, the width approximately the same as the height.

12. The semiconductor device of claim 10 , wherein each of the nanowires consists essentially of silicon, and the entire perimeter of each of the source and drain regions is an exposed <111> silicon surface.

13. The semiconductor device of claim 10 , further comprising:
a doping layer disposed on and completely surrounding the perimeter of each of the source and drain regions, between the source and drain regions and the pair of conductive contacts.

14. The semiconductor device of claim 10 , wherein the gate electrode stack comprises a metal gate and a high-K gate dielectric, and each of the nanowires comprises silicon, germanium, or a combination thereof.

15. The semiconductor device of claim 10 , wherein each of the channel regions has a width and a height, the width substantially greater than the height, and wherein each of the source and drain regions has a width and a height, the width substantially greater than the height.

16. The semiconductor device of claim 15 , wherein each of the nanowires consists essentially of silicon, the perimeter along the width of each of the source and drain regions comprises exposed <110> silicon surfaces, and the perimeter along the height of each of the source and drain regions comprises exposed <100> silicon surfaces.

17. The semiconductor device of claim 10 , wherein each of the channel regions has a width and a height, the width substantially less than the height, and wherein each of the source and drain regions has a width and a height, the width substantially less than the height.

18. The semiconductor device of claim 17 , wherein each of the nanowires consists essentially of silicon, the perimeter along the width of each of the source and drain regions comprises exposed <100> silicon surfaces, and the perimeter along the height o

Assignees

• Cea Stephen M
• Weber Cory E
• Keys Patrick H
• Kim Seiyon
• Haverty Michael G
• Shankar Sadasivan
• Intel Corp

Inventors

• Cea Stephen M
• Weber Cory E
• Keys Patrick H
• Kim Seiyon
• Haverty Michael G
• Shankar Sadasivan

Classifications

• B82Y10/00 Primary

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• H01L29/0673

  Electricity · mapped topic

• H01L29/66439

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic