Victim cache that supports draining write-miss entries
US-2024264952-A1 · Aug 8, 2024 · US
US9208024B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9208024-B2 |
| Application number | US-201414152926-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 10, 2014 |
| Priority date | Jan 10, 2014 |
| Publication date | Dec 8, 2015 |
| Grant date | Dec 8, 2015 |
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A method and apparatus are provided for error correction of a memory by using a first memory ( 18 ) and second memory ( 14 ) to perform error correction code (ECC) processing on data retrieved from the first memory and to use status control bits ( 35 - 37 ) in the second memory to detect and manage hard and soft errors identified by the ECC processing.
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What is claimed is: 1. A method comprising: initiating a read operation of a first memory to retrieve data from a specified address; performing an error correction code (ECC) process on the data to detect if the data is erroneous and to provide corrected data; storing the specified address and corrected data in a second memory in an available entry and setting a first status bit for the available entry in the second memory; at a first predetermined time after storing the spe…
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