Boundary based power guidance for physical synthesis

Patent metadata

Field	Value
Publication number	US-9471735-B2
Application number	US-201514961962-A
Country	US
Kind code	B2
Filing date	Dec 8, 2015
Priority date	Feb 20, 2014
Publication date	Oct 18, 2016
Grant date	Oct 18, 2016

Abstract

A method and system to obtain a physical design of an integrated circuit from a logical design are described. The system includes a memory device to store a logical design, and a processor to execute a synthesis engine. The processor performs a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget, computes power assertions, performs a re-synthesis using the timing constraints and the power assertions to obtain a new physical design, compares the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design, reduces a weighting of the power assertions relative to the timing constraints based on the degradation, and iteratively performs the re-synthesis, compares the new physical design with the baseline physical design, and reduces the weighting until the degradation is below a threshold value.

First claim

What is claimed is:

1. A system to obtain a physical design of an integrated circuit from a logical design, the system comprising:
a memory device configured to store a logical design; and
a processor configured to execute a synthesis engine, the processor being further configured to:
perform a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget;
compute power assertions;
perform a re-synthesis using the timing constraints and the power assertions to obtain a new physical design;
compare the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design;
reduce a weighting of the power assertions relative to the timing constraints based on the degradation; and
iteratively perform the re-synthesis, compare the new physical design with the baseline physical design, and reduce the weighting until the degradation is below a threshold value.

2. The system according to claim 1 , wherein the processor is configured to compute the power assertions based on propagating a computation of power cost for nodes in the integrated circuit in a first direction.

3. The system according to claim 2 , wherein the processor is configured to compute the power assertion based on propagating a computation of power slack for the nodes in a second direction, the second direction being opposite the first direction.

4. The system according to claim 1 , wherein the processor is configured to perform the re-synthesis by selecting a technique based on the power assertions and the weighting of the power assertions.

5. The system according to claim 4 , wherein the technique corresponds with a range of threshold voltage values and drive strength values targeted by the processor in performing the re-synthesis.

6. The system according to claim 5 , wherein the technique is selected from a standard cell library.

7. A computer program product storing instructions which, when executed by a processor, cause the processor to implement a method of obtaining a physical design of an integrated circuit from a logical design, the method comprising:
performing a baseline synthesis to obtain a baseline physical design using timing constraints and an overall power budget;
computing power assertions;
performing a re-synthesis using the timing constraints and the power assertions to obtain a new physical design;
comparing the new physical design with the baseline physical design to determine a degradation of the new physical design in comparison with the baseline physical design;
reducing a weighting of the power assertions relative to the timing constraints based on the degradation; and
iteratively executing the performing the re-synthesis, the comparing, and the reducing until the degradation is below a threshold value.

8. The computer program product according to claim 7 , wherein the computing the power assertions includes propagating a computation of power cost for nodes in the integrated circuit in a first direction.

9. The computer program product according to claim 7 , wherein the computing the power assertions includes propagating a computation of power slack for the nodes in a second direction, the second direction being opposite the first direction.

10. The computer program product according to claim 7 , wherein the performing the re-synthesis includes selecting a technique based on the power assertions and the weighting of the power assertions.

11. The computer program product according to claim 10 , wherein the technique corresponds with a range of threshold voltage values and drive strength values targeted by the performing the re-synthesis.

12. The computer program product according to claim 11 , wherein the technique is selected from a standard cell library.

Assignees

• IBM

Inventors

• Chakrabarti Pinaki
• Guha Kaustav
• Nigaglioni Ricardo H
• Saha Sourav

Classifications

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F17/505 Primary

  Physics · mapped topic

• G06F17/5081

  Physics · mapped topic