Approach for performing improved timing analysis with improved accuracy

Patent metadata

Field	Value
Publication number	US-9659139-B2
Application number	US-201514744012-A
Country	US
Kind code	B2
Filing date	Jun 18, 2015
Priority date	Jun 18, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

One embodiment of the present invention includes a method for updating timing parameters after a circuit design change. The method includes, prior to the circuit design change, deriving a value for a first timing parameter based on a signoff timing analysis of a timing arc, and a value for a second timing parameter based on a quick timing analysis of the timing arc; and obtaining a first transition time based on the quick timing analysis. The method further includes, after the circuit design change, deriving a value for a third timing parameter based on the quick timing analysis, obtaining a second transition time based on the quick timing analysis, and deriving a fourth value for a fourth parameter based on the quick timing analysis, wherein the fourth parameter is based on the first, second, and third parameters and on the first and second transition times.

First claim

What is claimed is:

1. A non-transitory computer-readable storage medium including instructions that, when executed by a processor, cause the processor to update one or more timing parameters included in a plurality of timing parameters after a circuit design change associated with a very large scale integrated (VLSI) circuit, by performing the steps of:
prior to the circuit design change:
deriving a first value for a first timing parameter included in the plurality of timing parameters based on a signoff timing analysis of a timing arc included in a plurality of timing arcs associated with the VLSI circuit,
deriving a second value for a second timing parameter included in the plurality of timing parameters based on a first quick timing analysis of the timing arc, and
obtaining a first transition time based on the first quick timing analysis; and

after the circuit design change:
deriving a third value for a third timing parameter included in the plurality of timing parameters based on a second quick timing analysis of the timing arc,
obtaining a second transition time based on the second quick timing analysis,
deriving a fourth value for a fourth timing parameter included in the plurality of timing parameters based on the first timing parameter, the second timing parameter, the third timing parameter, the first transition time and the second transition time and
generating a timing analysis for each timing arc included in the plurality of timing arcs associated with the VLSI circuit design based at least on the fourth timing parameter.

2. The computer-readable storage medium of claim 1 , wherein the fourth timing parameter comprises a calibrated result of the quick timing analysis that closely matches a signoff analysis result related to the circuit design change, and the fourth timing parameter is related to an empirically derived parameter that is dependent on a particular manufacturing process.

3. The computer-readable storage medium of claim 1 , wherein at least one of the first timing parameter and the second timing parameter comprises an arrival time or a transition time associated with the timing arc.

4. The computer-readable storage medium of claim 1 , wherein the fourth timing parameter is further based on a first ratio of the second transition time to the first transition time, the first ratio raised to a power, and a difference between the second and first timing parameters.

5. The computer-readable storage medium of claim 1 , wherein the circuit design includes a logic gate, a wire, and a first buffer along the wire; and wherein the circuit design change includes at least one of a change to a size of the logic gate, a placement of the logic gate, an addition of a second buffer along the wire, a removal of the first buffer, a removal of the second buffer and a change to a size of the wire.

6. The computer-readable storage medium of claim 1 , wherein the circuit design includes at least one circuit element having at least one input pin and an output pin; and further including instructions that, when executed by a processor, cause the processor to perform the step of computing a slack time for the at least one input pin.

7. The computer-readable storage medium of claim 6 , wherein the slack time is based on a slack offset value relative to an arrival difference value, the slack offset value being a difference between a computed slack time and a slack time obtained from the signoff analysis, and the arrival time difference value being a difference between a first arrival time obtained from the signoff analysis and a second arrival time obtained from the quick timing analysis.

8. The computer-readable storage medium of claim 6 , wherein the circuit element comprises a first input pin and a second input pin, wherein each of the first input pin and the second input pin is associated with a different arrival time and a different slack time; and further including instructions that, when executed by a processor, cause the processor to perform the step of computing a slack offset based on a first difference between a slack time related to the first input pin and a slack time related to the output pin and on a second difference between a slack time related to the second input pin and the slack time related to the output pin.

9. The computer-readable storage medium of claim 1 , wherein the timing arc is included in a plurality of timing arcs, and further including instructions that, when executed by a processor, cause the processor to perform the step of propagating an update caused by a difference between the fourth timing parameter and the third timing parameter to one or more other timing arcs included in the plurality of timing arcs.

10. The computer-readable storage medium of claim 9 , wherein propagating the update to the one or more other timing arcs stops when a magnitude of the update falls below a threshold value.

11. The computer-readable storage medium of claim 9 , wherein propagating the update to the one or more other timing arcs stops when a timing endpoint is reached.

12. A method performed by a computer for updating one or more timing parameters included in a plurality of timing parameters after a circuit design change associated with a very large scale integrated (VLSI) circuit, the method comprising:
prior to the circuit design change:
deriving a first value for a first timing parameter included in the plurality of timing parameters based on a signoff timing analysis of a timing arc,
deriving a second value for a second timing parameter included in the plurality of timing parameters based on a first quick timing analysis of the timing arc, and
obtaining a first transition time based on the first quick timing analysis; and

after the circuit design change:
deriving a third value for a third timing parameter included in the plurality of timing parameters based on a second quick timing analysis of the timing arc,
obtaining a second transition time based on the second quick timing analysis,
deriving, via a processor, a fourth value for a fourth timing parameter included in the plurality of timing parameters based on the first timing parameter, the second timing parameter, the third timing parameter, the first transition time and the second transition time, and
generating a timing analysis for each timing arc included in the plurality of timing arcs associated with the VLSI circuit design based at least on the fourth timing parameter.

13. The method of claim 12 , wherein the fourth timing parameter is further based on a first ratio of the second transition time to the first transition time, the first ratio raised to a power, and a difference between the second and first timing parameters.

14. The method of claim 12 , wherein the circuit design includes at least one circuit element having at least one input pin and an output pin; and further comprising computing a slack time for the at least one input pin.

15. The method of claim 14 , wherein the slack time is based on a slack offset value relative to an arrival difference value, the slack offset value being a difference between a computed slack time and a slack time obtained from the signoff analysis, and the arrival time difference value being a difference between a first arrival time obtained from the signoff analysis and a second arrival time obtained from the quick timing analysis.

16. A timing analysis system, comprising:
a memory storing a timing analysis application; and
a processor coupled to the memory, wherein, when executed by the processor,
the timing analysis application configures the processor to:
prior t

Assignees

• Nvidia Corp

Inventors

• Brown David Lyndell

Classifications

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F2119/10

  Noise analysis or noise optimisation · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F30/30

  Circuit design · CPC title