Reconfigurable physically unclonable functions based on analog non-volatile memories

Patent metadata

Field	Value
Publication number	US-10812084-B2
Application number	US-201916676101-A
Country	US
Kind code	B2
Filing date	Nov 6, 2019
Priority date	Nov 6, 2018
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

A security primitive for an integrated circuit comprises an array of floating-gate transistors monolithically integrated into the integrated circuit and coupled to one another in a crossbar configuration. The floating-gate transistors have instance-specific process-induced variations in analog behavior to provide one or more reconfigurable physically unclonable functions (PUFs).

First claim

The invention claimed is:

1. A security primitive for an integrated circuit, comprising:
an array of floating-gate transistors monolithically integrated into the integrated circuit and coupled to one another in a crossbar configuration, wherein the respective floating-gate transistors have instance-specific process-induced variations in analog behavior to provide one or more reconfigurable physically unclonable functions (PUFs); and
peripheral circuitry coupled to the array of floating-gate transistors, the peripheral circuitry being configured to apply a voltage to selected ones of the floating-gate transistors for generating an unpredictable nonlinear combination of input currents through the selected floating-gate transistors.

2. The security primitive of claim 1 , wherein the variations in analog behavior comprise variations in nonlinear conductances of the floating-gate transistors.

3. The security primitive of claim 1 , wherein the variations in analog behavior comprise one or more of leakage current variations, subthreshold I-V slope variations, nondeterministic tuning error, or sneak path current variations.

4. The security primitive of claim 1 , wherein each of the floating-gate transistors comprises a split-gate NOR flash memory cell.

5. The security primitive of claim 1 ,
wherein the array of floating-gate transistors comprises an n×(m−n) array, where m represents one of a row or column, and (m−n) represents the other of the row or column;
wherein the crossbar configuration comprises:
n source lines, each source line connecting (m−n) floating-gate transistors;
n pairs of word lines opposing one another with respect to the source line and connecting the (m−n) floating-gate transistors;

wherein the crossbar configuration further comprises:
(m−n) bit lines, each bit line connecting n floating-gate transistors.

6. The security primitive of claim 5 ,
wherein each of the floating-gate transistors comprises:
a source coupled to one of the n source lines;
first and second control gates disposed between the pair of word lines and opposing one another with respect to the source; and
first and second floating gates disposed between the pair of word lines and respectively associated with the first and second control gates.

7. The security primitive of claim 6 , wherein the crossbar configuration further comprises n erase-gate lines, each of the n erase-gate lines connecting (m−n) floating gate transistors.

8. The security primitive of claim 6 , wherein the peripheral circuitry comprises:
a row switching block coupled to the array of floating-gate transistors and configured to selectively switch rows of the array of floating-gate transistors in response to a first set of bits of an input challenge;
a column switching block coupled to the array of floating-gate transistors and configured to selectively switch rows of the array of floating-gate transistors in response to a second set of bits of the input challenge;
biasing circuitry configured to apply the voltage to selected rows and/or columns of the array of floating-gate transistors; and
output circuitry configured to selectively receive input currents from rows or columns of the array of floating-gate transistors and generate an output bit based on the received input currents.

9. The security primitive of claim 8 , wherein the output circuitry receives input currents from selected source lines.

10. The security primitive of claim 8 , wherein the output circuitry receives input currents selected in response to a third set of bits of the input challenge.

11. An integrated circuit, comprising:
at least one security primitive configured to receive an input challenge and generate at least one output bit, each security primitive comprising:
an array of floating-gate transistors monolithically integrated into the integrated circuit and coupled to one another in a crossbar configuration, wherein the respective floating-gate transistors have instance-specific process-induced variations in analog behavior to provide one or more reconfigurable physically unclonable functions (PUFs);

a row switching block coupled to the array of floating-gate transistors and configured to selectively switch rows of the array of floating-gate transistors in response to a first set of bits of the input challenge;
a column switching block coupled to the array of floating-gate transistors and configured to selectively switch rows of the array of floating-gate transistors in response to a second set of bits of the input challenge;
biasing circuitry configured to apply a voltage to selected rows and/or columns of the array of floating-gate transistors; and
output circuitry configured to selectively receive input currents from rows or columns of the array of floating-gate transistors and generate the at least one output bit based on the received input currents.

12. The integrated circuit of claim 11 , further comprising:
a clock signal generator for generating at least a first clock signal for receiving bits of the input challenge and a second clock signal for generating the at least one output bit.

13. The integrated circuit of claim 11 , wherein the integrated circuit comprises a plurality of the security primitives arranged in at least one layer.

14. The integrated circuit of claim 13 , wherein the plurality of security primitives are arranged in a plurality of layers.

15. The integrated circuit of claim 14 , further comprising:
a clock signal generator for generating at least a first clock signal for receiving bits of the input challenge and a second clock signal for generating the at least one output bit to provide time-domain multiplexing.

16. The integrated circuit of claim 15 , wherein the plurality of layers comprise first and second layers of security primitives, and wherein the integrated circuit further comprises:
a bit processor for receiving output bits from the first layer of security primitives, processing the received output bits, and inputting the processed bits to the second layer of security primitives.

17. The integrated circuit of claim 16 , wherein the bit processor comprises one or more of a shift register, a bit concatenator, or an XOR bit combiner.

18. The integrated circuit of claim 17 , further comprising:
one or more additional bit processors configured to receive bits of the input challenge, processes the received bits, and distribute the processed bits among at least the row switching blocks and the column switching blocks of the security primitives in the first layer.

19. A method for generating one or more output bits from an input challenge applied to an integrated circuit, the integrated circuit comprising an array of floating-gate transistors monolithically integrated into the integrated circuit and coupled to one another in a crossbar configuration, wherein the respective floating-gate transistors have instance-specific process-induced variations in analog behavior to provide one or more reconfigurable physically unclonable functions (PUFs), the integrated circuit further comprising peripheral circuitry coupled to the array of floating-gate transistors, the peripheral circuitry being configured to apply a voltage to selected ones of the floating-gate transistors for generating an unpredictable nonlinear combination of input currents through the selected floating-gate transistors, wherein the method comprises:
tuning voltage thresholds of the array of floating-gate transistors;
inputting bits of the input challenge to the integrated circuit includi

Assignees

• Univ California

Inventors

• Strukov Dmitri
• Ahmadabadi Hussein Nili
• Mahmoodi Mohammad Reza
• Fahimi Zahra

Classifications

• G11C7/16

  Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters · CPC title

• H03K19/17768 Primary

  for security · CPC title

• H04L9/0866

  involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics · CPC title

• H03K19/17756 Primary

  for partial configuration or partial reconfiguration · CPC title

• H04L9/3278

  using physically unclonable functions [PUF] · CPC title