Non-volatile memory array with memory gate line and source line scrambling

Patent metadata

Field	Value
Publication number	US-9997253-B1
Application number	US-201715471418-A
Country	US
Kind code	B1
Filing date	Mar 28, 2017
Priority date	Dec 8, 2016
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.

First claim

What is claimed is:

1. A memory device, comprising:
a memory array arranged in rows and columns, including,
at least four non-volatile memory (NVM) cells coupled in a same column of the memory array, wherein each NVM cell includes a memory gate, and wherein first and second NVM cells of the at least four NVM cells share a first source line and third and fourth NVM cells share a second source line, wherein the first and second source lines are adjacent to one another,
wherein the memory gates of the first and second NVM cells are not electrically coupled with one another, wherein the first and second source lines are not electrically coupled with one another, and wherein each of the first and second source lines is physically connected with at least one source line of the same column that is not the first and second source lines.

2. The memory device of claim 1 , wherein the memory array is at least partly formed by coupling a plurality of the at least four NVM cells, wherein a first plurality of the at least four NVM cells are coupled to form a first column of the memory array, and wherein pattern of the first column is repeated in at least one remaining columns of the memory array.

3. The memory device of claim 2 , wherein configurations of the rows and the columns of the memory array are reversed.

4. The memory device of claim 1 , wherein the first and second NVM cells include a mirrored orientation, the first and second memory gates face one another, and the first source line disposed between the first and second memory gates, and wherein the third and fourth NVM cells include the mirrored orientation, the third and fourth memory gates face one another, and the second source line disposed between the third and fourth memory gates.

5. The memory device of claim 1 , wherein the at least four NVM cells include a split gate memory cell configuration.

6. The memory device of claim 1 , wherein the at least four NVM cells include a two-transistor memory cell configuration, and wherein the two-transistor memory cell includes one field-effect-transistor, and one silicon-oxide-nitride-oxide-silicon transistor or one floating gate transistor.

7. The memory device of claim 1 , wherein when the first memory cell is selected for a program operation and the second memory cell is not selected for the program operation, the first and second memory gates are configured to receive a high voltage and a low voltage from two different memory gate driver circuits, respectively.

8. The memory device of claim 1 , wherein when the second memory cell is selected for a program operation and the third memory cell is not selected for the program operation, the second and third memory gates are configured to receive a high voltage, wherein the first and second source lines are configured to receive a high source voltage and a low source voltage, respectively from two different source line driver circuits.

9. The memory device of claim 8 , wherein the high voltage is in an approximate range of 5 V to 10 V, and the low voltage in an approximate range of 0 V to 5 V.

10. A memory array, comprising:
non-volatile memory (NVM) cells, each including a memory gate and a select gate, arranged in rows and columns, wherein,
two adjacent NVM cells of a same column that share a source region form an NVM pair, wherein the source region is disposed between memory gates of the two adjacent NVM cells, and wherein multiple NVM pairs are coupled to one another in the same column,
at least two memory gates of NVM cells of a same row share a memory gate line,
at least two source regions of NVM cells of the same row share a source line; and
source line connection routing configured to connect multiple source lines physically and electrically to form multiple source line groups, wherein the multiple source lines in a same source line group are not physically adjacent to one another.

11. The memory array of claim 10 , wherein:
at least two select gates of NVM cells of the same row share a select gate line; and
at least two drain regions of NVM cells of the same column share a bit line, wherein the drain region of each of the NVM cells is disposed adjacent to the select gate.

12. The memory array of claim 10 , wherein each of the multiple source line groups is coupled with a separate source line driver circuit, configured to receive a separate source voltage.

13. The memory array of claim 10 , further comprising:
memory gate connection routing configured to connect multiple memory gate lines electrically to form multiple memory gate line groups, wherein the multiple memory gate lines in a same memory gate line group do not share any source line that is in a same source line group, and wherein each of the multiple memory gate line groups is coupled with a separate memory gate line driver circuit, configured to receive a separate memory gate voltage.

14. The memory array of claim 13 , wherein the NVM cells in the multiple source lines in a same source line group do not include memory gate lines that are in the same memory gate line group.

15. The memory array of claim 10 comprising 2N rows of NVM cells, N being a natural number, wherein:
multiple odd source lines including 1 st to (N−1) th source lines are connected electrically by a first source line connection routing;
multiple even source lines including 0 th to (N−2) th source lines are connected electrically by a second source line connection routing; and
the first and second source line connection routings are coupled to two different source line driver circuits.

16. The memory array of claim 10 comprising 2N rows of NVM cells, N being a natural number, wherein:
0 th and (2N−1) th memory gate lines are connected electrically by a first memory gate line connection routing;
at least one remaining odd memory gate line is connected electrically to its adjacent even memory gate line by a second memory gate line connection routing; and
the first and the second memory gate line connection routing are each coupled to a separate memory gate driver circuit.

17. The memory array of claim 13 , wherein the memory gate connection routing includes metal 1 (M1) connection to the memory gate driver circuit.

18. The memory array of claim 10 , wherein the NVM cells include two-transistor memory cells.

19. The memory array of claim 10 , wherein the NVM cells include split gate memory cells.

20. A method, comprising:
providing a non-volatile memory (NVM) array, wherein the non-volatile memory array includes at least four non-volatile memory (NVM) cells coupled in a same column of the NVM array, wherein each NVM cell includes a memory gate and a select gate, wherein first and second NVM cells of the at least four NVM cells share a first source line, and third and fourth NVM cells share a second source line, and wherein the first and second source lines are each physically connected with at least another source line that is not physically adjacent to the first and second source lines respectively;
coupling a high select voltage to a first select gate to select the first memory cell for a program operation;
coupling a low select voltage to a second select gate to unselect the second memory cell for the program operation;
coupling a high program voltage to the first memory gate and a low inhibit voltage to the second memory gate; and
coupling two different source voltages to the first source line and the second source line from two different source line driver circuits, respectively.

21. The

Assignees

• Cypress Semiconductor Corp

Inventors

• Chen Chun
• Betser Yoram
• Chang Kuo-Tung
• Givant Amichai
• Shetty Shivananda
• Fang Shenqing

Classifications

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title