Tamper-resistant non-volatile memory device comprising an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, a read circuit that, in operation, selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information, and a write circuit that, in operation, performs a write operation corresponding to one of the two values among memory cells

Patent metadata

Field	Value
Publication number	US-9653161-B2
Application number	US-201514938755-A
Country	US
Kind code	B2
Filing date	Nov 11, 2015
Priority date	Nov 21, 2014
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A non-volatile memory device includes a memory cell array including memory cells, each having a resistance value reversibly transitioning among resistance value ranges, a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells, an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, and a write circuit. In operation, the read circuit selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information. In operation, the write circuit performs a first write operation on a memory cell corresponding to one of the two values among the memory cells.

First claim

What is claimed is:

1. A non-volatile memory device comprising:
a memory cell array including memory cells arranged in an array, each of the memory cells having a resistance value and having a property that the resistance value reversibly transitions among resistance value ranges in a non-volatile manner in a variable state in accordance with application of different electrical signals;
a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells;
an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information; and
a write circuit, wherein, in operation,
the read circuit selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information, thereby generating pieces of digital data, and
the write circuit performs a first write operation on a memory cell corresponding to one of the two values among the memory cells.

2. The non-volatile memory device according to claim 1 , wherein
the resistance value ranges include a first resistance value range and a second resistance value range lower than the first resistance value range,
in an initial state, the resistance value of each of the memory cells is within an initial resistance value range different from the first resistance value range and the second resistance value range,
each of the memory cells changes from the initial state to the variable state by application of an electrical stress to each of the memory cells,
in the variable state, the resistance value of each of the memory cells transitions from the second resistance value range to the first resistance value range by application of a voltage pulse having a first polarity to each of the memory cells, and the resistance value of each of the memory cells transitions from the first resistance value range to the second resistance value range by application of a voltage pulse having a second polarity to each of the memory cells, and
in the first write operation, the write circuit alternately applies a first voltage pulse having the first polarity and a second voltage pulse having the second polarity to a memory cell corresponding to one of the two values among the memory cells.

3. The non-volatile memory device according to claim 2 , wherein the resistance values of one half or more of a number of memory cells corresponding to the pieces of digital data are within the second resistance value range.

4. The non-volatile memory device according to claim 1 , wherein, in operation, the arithmetic circuit calculates a median value of the pieces of resistance value information, which is obtained by the read circuit, as the binary reference value.

5. The non-volatile memory device according to claim 4 , wherein, in operation, the write circuit performs the first write operation on a memory cell whose resistance value is lower than the median value among the memory cells.

6. The non-volatile memory device according to claim 2 , wherein, in operation,
the write circuit performs a second write operation on each of the memory cells that are in the initial state, the second write operation including alternately applying a third voltage pulse having the first polarity and a fourth voltage pulse having the second polarity,
the read circuit reads resistance value information on each of the memory cells on which the second write operation has been performed, and determines, based on the resistance value information, whether or not the resistance value of each of the memory cells on which the second write operation has been performed is within the second resistance value range, and
the write circuit and the read circuit repeatedly perform the second write operation and the reading of the resistance value information until it is determined that the resistance value of each of the memory cells on which the second write operation has been performed is within the second resistance value range.

7. The non-volatile memory device according to claim 1 , wherein the read circuit includes a comparison circuit that, in operation, compares the resistance value indicated by each of the pieces of resistance value information obtained by the read circuit with the binary reference value and that outputs binary data of 0 or 1 in accordance with a result of comparison.

8. The non-volatile memory device according to claim 1 , further comprising a generation circuit that, in operation, generates mask data used to distinguish a memory cell on which the first write operation is performed among the memory cells from a memory cell on which the first write operation is not performed among the memory cells, in accordance with the pieces of digital data generated by the read circuit.

9. The non-volatile memory device according to claim 8 , wherein, in operation, the write circuit performs, based on the mask data, the first write operation on a memory cell on which the first write operation is performed.

10. The non-volatile memory device according to claim 1 , further comprising a control circuit, wherein
the first write operation is an operation for applying a voltage pulse to a memory cell corresponding to one of the two values among the memory cells, and
the control circuit, in operation, modifies at least one selected from the group consisting of the number of times the voltage pulse is applied, a voltage of the voltage pulse, and a pulse width of the voltage pulse in the first write operation.

11. The non-volatile memory device according to claim 10 , wherein
the memory cells is divided into a first group and a second group, and
the at least one selected from the group consisting of the number of times the voltage pulse is applied, the voltage of the voltage pulse, and the pulse width of the voltage pulse in the first write operation is different between a memory cell belonging to the first group and a memory cell belonging to the second group among the memory cells.

12. The non-volatile memory device according to claim 1 , further comprising a control circuit, wherein, in operation,
the control circuit accepts an input of a control signal, and
the read circuit obtains the pieces of resistance value information in accordance with the control signal input to the control circuit.

13. An integrated circuit card comprising:
a non-volatile memory device including
a memory cell array including memory cells arranged in an array, each of the memory cells having a resistance value and having a property that the resistance value reversibly transitions among resistance value ranges in a non-volatile manner in a variable state in accordance with application of different electrical signals,
a read circuit that, in operation, obtains pieces of resistance value information each relating to the resistance value of one of the memory cells,
an arithmetic circuit that, in operation, calculates a binary reference value based on at least a part of the pieces of resistance value information, and
a write circuit, wherein, in operation,
the read circuit selectively assigns, based on the binary reference value, one of two values to each of the pieces of resistance value information, thereby generating pieces of digital data, and
the write circuit performs a first write operation on a memory cell corresponding to one of the two values among the memory cells; and

an input/output interface unit to which a signal that controls an operation of the non-volatile memory device is input and from which information related to the pieces of digital data is output.

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Yoshimoto Yuhei
• Katoh Yoshikazu

Classifications

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C16/20

  Initialising; Data preset; Chip identification · CPC title

• G11C2013/0054

  Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title