Leadframe leads having fully plated end faces

Patent metadata

Field	Value
Publication number	US-10796986-B2
Application number	US-201615075266-A
Country	US
Kind code	B2
Filing date	Mar 21, 2016
Priority date	Mar 21, 2016
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

A semiconductor device includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulation material encapsulating the semiconductor die and a portion of the leadframe. The leadframe includes a first main face and a second main face opposite to the first main face. The leadframe includes leads wherein each lead includes a fully plated end face extending between an unplated first sidewall and an unplated second sidewall opposite to the first sidewall. The end face and the first and second sidewalls of each lead are perpendicular to the first and second main faces.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a leadframe comprising a first main face disposed entirely in a first plane and a second main face opposite to the first main face disposed entirely in a second plane, the leadframe comprising leads wherein each lead comprises a fully plated planar end face extending between an unplated first sidewall on a first side of the lead and an unplated second sidewall on a second side of the lead that is opposite to the unplated first sidewall, wherein the fully plated planar end face and the unplated first sidewall and the unplated second sidewall of each lead are perpendicular to the first and second main faces;
a semiconductor die attached to the leadframe; and
an encapsulation material encapsulating the semiconductor die and a portion of the leadframe and forming a plurality of side surfaces of the semiconductor device at an outline of the encapsulation material,
wherein each lead includes a bottom fully plated second main face interior to the outline and below the encapsulation material to improve the solderability of the fully plated second main face to a circuit board, wherein each lead extends from a side surface of the plurality of side surfaces and includes a plated first sidewall on the first side of the lead that is between the unplated first sidewall and the encapsulation material and a plated second sidewall on the second side of the lead that is between the unplated second sidewall and the encapsulation material, wherein each lead, on the first side of the lead, includes only the unplated first sidewall and the plated first sidewall, wherein each lead, on the second side of the lead, includes only the unplated second sidewall and the plated second sidewall, and
where the plated first sidewall is nonplanar with the unplated first sidewall, and where the plated second sidewall is nonplanar with the unplated second sidewall.

2. The semiconductor device of claim 1 , wherein the fully plated end face of each lead is plated with a material layer to improve the solderability of an end face of each lead.

3. The semiconductor device of claim 1 , wherein the leadframe comprises a metal, and
wherein the unplated first sidewall and the unplated second sidewall of each lead exposes the metal.

4. The semiconductor device of claim 1 , wherein the fully plated end face of each lead enables automated optical inspection of solder wetting between the leadframe and a circuit board.

5. The semiconductor device of claim 1 , wherein the portion of the leadframe to which the semiconductor die is attached is a die pad.

6. The semiconductor device of claim 5 , wherein the semiconductor die is electrically coupled to the die pad.

7. The semiconductor device of claim 1 , wherein the unplated first sidewall is planar and wherein the unplated second sidewall is planar and parallel to the unplated first sidewall.

8. The semiconductor device of claim 1 , wherein the plurality of side surfaces include first and second opposing side surfaces, and third and fourth opposing side surfaces, the third and fourth opposing side surfaces are perpendicular to the first and second opposing side surfaces, wherein leads extend from the first and second side surfaces and a tie bar extends from each of the third and fourth side surfaces.

9. The semiconductor device of claim 8 , wherein leads extending from the first side surface comprise a drain electrode and leads extending from the opposing second side surface comprises a source electrode and a gate electrode of the semiconductor die.

10. The semiconductor device of claim 1 , where the first plated sidewall and the second plated sidewall are curved.

11. The semiconductor device of claim 10 , where the first plated sidewall and the second plated sidewall are concave.

12. The semiconductor device of claim 1 , where the leads extend from at least one of the plurality of side surfaces.

13. The semiconductor device of claim 1 , comprising:
a tie bar extending from a side surface of the semiconductor device, the tie bar including an unplated tie bar end face and plated tie bar sidewalls.

14. A semiconductor device comprising:
a leadframe including a leadframe body and a plurality of leads extending from the leadframe body, each lead including a fully plated end face and a first sidewall on a first side of the lead and a second sidewall on a second side of the lead, the first sidewall and the second sidewall each extending between the fully plated end face and the leadframe body, the first sidewall including an unplated first sidewall and a plated first sidewall, where the plated first sidewall is nonplanar relative to the first unplated sidewall; and
an encapsulation material encapsulating at least a portion of the leadframe and forming a plurality of side surfaces of the semiconductor device at an outline of the encapsulation material, where the plurality of leads extend outward from the encapsulation material, wherein each lead includes a bottom fully plated second main face interior to the outline and below the encapsulation material to improve the solderability of the fully plated second main face to a circuit board, and wherein each lead, on the first side of the lead, includes only the unplated first sidewall and the plated first sidewall between the fully plated end face and the encapsulation material.

15. The semiconductor device of claim 14 , comprising:
a semiconductor die coupled to the lead frame.

16. The semiconductor device of claim 14 where the plated first sidewall is curved.

17. The semiconductor device of claim 16 , where the plated first sidewall is concave.

18. The semiconductor device of claim 14 , comprising:
where the second sidewall includes an unplated second sidewall and a plated second sidewall, where the plated second sidewall is nonplanar relative to the unplated second sidewall, wherein each lead, on the second side of the lead, includes only the unplated second sidewall and the plated second sidewall between the fully plated end face and the encapsulation material.

19. The semiconductor device of claim 14 , comprising:
a tie bar extending from the lead frame body, the tie bar including an unplated tie bar end face and plated tie bar sidewalls.

Assignees

• Infineon Technologies Ag

Inventors

• Macheiner Stefan
• Dinkel Markus

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P14/46

  using a liquid · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title