Quad flat non-leaded semiconductor package with wettable flank

Patent metadata

Field	Value
Publication number	US-9324637-B1
Application number	US-201514743986-A
Country	US
Kind code	B1
Filing date	Jun 18, 2015
Priority date	Dec 17, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A Quad Flat Non-leaded (QFN) semiconductor package has a semiconductor die mounted on a die flag of a lead frame. A molded housing with a base and sides covers the die. The package has electrically conductive mounting feet each of which includes an exposed base surface in the base of the housing, an opposite parallel surface covered by the housing, and an exposed end surface in the one of the sides of the housing. The exposed end surface is normal to, and located between, the exposed base surface and the opposite parallel surface. Bond wires selectively electrically connect electrodes of the die to respective ones of the mounting feet. An electrically conductive plating coats the exposed base portion and exposed end surface of the mounting feet.

First claim

The invention claimed is:

1. A method of assembling a Quad Flat Non-leaded (QFN) semiconductor package, the method comprising:
providing a populated housed lead frame sheet assembly of assembled QFN semiconductor packages, wherein each of the packages is formed from a lead frame comprising a surrounding frame that surrounds a die flag, tie bars extending inwardly from the surrounding frame and support the die flag and electrically conductive feet extending inwardly from the surrounding frame, and wherein a semiconductor die mounted on the die flag, bond wires selectively electrically connecting electrodes of the semiconductor die to respective ones of the feet, and a housing having a base and sides, the housing covering the semiconductor die, the flag, and partially covering the feet such that each of the feet includes an exposed base surface in the base of the housing and an opposite parallel surface covered by the housing;
partially separating each of the packages from each other to provide a partially separated sheet assembly of partially separated packages, the partially separating being performed by removing lengths of the surrounding frame to expose an end surface of each of the electrically conductive feet in the sides of the housing, wherein the exposed end surface is normal to, and located between, the exposed base surface and the opposite parallel surface;
mounting each of the partially separated packages to a respective electroplating mount, the electroplating mount having an electrically insulating body with conductive bars located along peripheral edges of the insulating body, and wherein the conductive bars electrically interconnect to the mounting feet that are located along the peripheral edge; and
plating the exposed end surface of each of the feet with an electrically conductive plating.

2. The method of claim 1 , wherein the plating comprises an electroplating process.

3. The method of claim 2 , wherein current is passed through the conductive bars during the electroplating process.

4. The method of claim 1 , wherein the electroplating mount includes interconnecting runners coupling the conductive bars together.

5. The method of claim 1 , wherein the conductive bars form a peripheral frame.

6. The method of claim 5 , wherein the peripheral frame includes recessed corner regions.

7. The method of claim 6 , wherein the recessed corner regions are encased in the electrically insulating body of the electroplating mount.

8. The method of claim 6 , wherein the exposed base portion is parallel to the base of the housing.

9. The method of claim 5 , wherein the interconnecting runners in plan view form a cross and wherein a central intersecting region of the cross is recessed.

10. The method of claim 9 , wherein the interconnecting runners are encased in the electrically insulating body of the electroplating mount.

11. The method of claim 1 , further comprising dismounting the partially separated packages from their respective electroplating mount.

12. The method of claim 11 , further comprising completely separating each of the packages from each other to provide QFN semiconductor packages.

13. The method of claim 12 , wherein the completely separating each of the packages comprises sawing or cutting the housing.

14. The method of claim 1 , wherein the lead frame comprises Palladium coated Copper and the electrically conductive plating material comprises Tin.

Assignees

• Freescale Semiconductor Inc

Inventors

• Bai Zhigang
• Pang Xingshou
• Xu Nan
• Yao Jinzhong

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title