Semiconductor device and method

Patent metadata

Field	Value
Publication number	US-10790244-B2
Application number	US-201815881362-A
Country	US
Kind code	B2
Filing date	Jan 26, 2018
Priority date	Sep 29, 2017
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

In an embodiment, a device includes: a conductive shield on a first dielectric layer; a second dielectric layer on the first dielectric layer and the conductive shield, the first and second dielectric layers surrounding the conductive shield, the second dielectric layer including: a first portion disposed along an outer periphery of the conductive shield; a second portion extending through a center region of the conductive shield; and a third portion extending through a channel region of the conductive shield, the third portion connecting the first portion to the second portion; a coil on the second dielectric layer, the coil disposed over the conductive shield; an integrated circuit die on the second dielectric layer, the integrated circuit die disposed outside of the coil; and an encapsulant surrounding the coil and the integrated circuit die, top surfaces of the encapsulant, the integrated circuit die, and the coil being level.

First claim

What is claimed is:

1. A method comprising:
depositing a conductive layer on a first dielectric layer;
etching the conductive layer to form a conductive shield on the first dielectric layer, the conductive shield comprising an opening and a first channel region, the first channel region connecting the opening to an outer edge of the conductive shield;
forming a second dielectric layer on the conductive shield;
forming a coil on the second dielectric layer, a center of the coil aligned with a center of the opening of the conductive shield, the coil being a continuous conductive spiral on a top surface of the second dielectric layer, the continuous conductive spiral winding around the center of the coil at continually increasing distances from the center of the coil;
placing an integrated circuit die on the second dielectric layer, the integrated circuit die disposed outside of the coil, the integrated circuit die comprising a die connector;
encapsulating the coil and the integrated circuit die with an encapsulant;
planarizing the encapsulant, the coil comprising a through via extending through the encapsulant after the planarizing, topmost surfaces of the through via, the die connector, and the encapsulant being coplanar; and
forming a redistribution structure on the topmost surfaces of the through via, the die connector, and the encapsulant.

2. The method of claim 1 , wherein the depositing the conductive layer comprises:
depositing a titanium layer on the first dielectric layer; and
depositing a copper layer on the titanium layer.

3. The method of claim 2 , wherein the etching the conductive layer comprises:
etching the copper layer with dilute phosphoric acid (H 3 PO 4 ) for a first time period of from about 20 seconds to about 40 seconds; and
etching the titanium layer with hydrofluoric acid (HF) for a second time period of from about 20 seconds to about 60 seconds.

4. The method of claim 1 , wherein no other conductive materials are formed on the conductive shield before forming the second dielectric layer on the conductive shield.

5. The method of claim 1 , further comprising:
placing a dummy semiconductor structure on the second dielectric layer directly over the opening of the conductive shield.

6. The method of claim 1 , wherein the forming the redistribution structure on the topmost surfaces of the through via, the die connector, and the encapsulant comprises:
forming metallization patterns in the redistribution structure, the metallization patterns electrically connecting the integrated circuit die to a first end of the coil and a second end of the coil.

7. The method of claim 1 , further comprising:
attaching a ferrite material to the redistribution structure, the ferrite material directly over the coil.

8. The method of claim 1 , further comprising:
attaching an external device to the redistribution structure, the external device electrically connected to the integrated circuit die.

9. A method comprising:
depositing a first dielectric layer;
forming a conductive shield on the first dielectric layer, the conductive shield comprising an opening and a first channel region, the first channel region extending from the opening to an outer edge of the conductive shield;
depositing a second dielectric layer on the conductive shield and the first dielectric layer;
forming a coil on the second dielectric layer, the coil being a series of conductive segments that wind around a fixed center point at continuously increasing distances from the fixed center point, the fixed center point disposed directly over the opening of the conductive shield, the second dielectric layer extending contiguously between the coil and the conductive shield;
placing an integrated circuit die on the second dielectric layer, the integrated circuit die comprising a first die connector, a second die connector, and a third dielectric layer, the first die connector and the second die connector each extending through the third dielectric layer; and
encapsulating the coil and the integrated circuit die with an encapsulant, topmost surfaces of the encapsulant, the first die connector, the second die connector, the third dielectric layer, and the coil being planar, wherein each of the conductive segments of the coil extend through the encapsulant after the planarizing.

10. The method of claim 9 , wherein the integrated circuit die is disposed outside of the coil, the encapsulant separating the coil from the integrated circuit die, and wherein the conductive segments of the coil form a continuous copper spiral, the continuous copper spiral emanating from a first end and terminating at a second end, the first end and the second end of the continuous copper spiral electrically connected to the integrated circuit die.

11. A method comprising:
depositing a conductive layer on a first dielectric layer;
patterning a mask on the conductive layer, the mask having an opening and a first channel region connecting the opening to an outer edge of the mask;
etching the conductive layer using the patterned mask as an etching mask, remaining portions of the conductive layer forming a conductive shield;
depositing a second dielectric layer on the conductive shield;
forming a coil on the second dielectric layer, a center of the coil aligned with a center of the opening of the conductive shield in a plan view, the second dielectric layer physically separating the coil from the conductive shield, the coil comprising conductive vias, the conductive vias winding around the center of the coil at continually increasing distances from the center of the coil;
placing an integrated circuit die on the second dielectric layer, the integrated circuit die comprising a die connector;
encapsulating the conductive vias and the integrated circuit die with an encapsulant; and
planarizing the encapsulant, the conductive vias, and the die connector such that topmost surfaces of the encapsulant, the conductive vias, and the die connector are coplanar.

12. The method of claim 11 , wherein the conductive vias of the coil form a continuous copper spiral, the continuous copper spiral emanating from a first end and terminating at a second end.

13. The method of claim 12 further comprising:
placing a dummy semiconductor structure on the second dielectric layer at the center of the continuous copper spiral.

14. The method of claim 12 further comprising:
depositing a third dielectric layer on the encapsulant;
patterning the third dielectric layer with a first opening and a second opening, the first opening exposing the first end of the continuous copper spiral, the second opening exposing the second end of the continuous copper spiral; and
forming a metallization pattern having a first portion extending through the first opening and a second portion extending through the second opening, the metallization pattern electrically connecting the integrated circuit die to the continuous copper spiral.

15. The method of claim 11 , wherein the etching the conductive layer comprises:
etching the conductive layer with dilute phosphoric acid (H 3 PO 4 ) for a first time period of from about 20 seconds to about 40 seconds; and
etching the conductive layer with hydrofluoric acid (HF) for a second time period of from about 20 seconds to about 60 seconds.

16. The method of claim 11 , wherein the first channel region is one of a plurality of channel regions in the mask, each one of the channel regions extending between the opening and the outer edge of the mask.

17. The method of claim 11 , wherein the opening in th

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Tzu-Sung
• Yu Chen-Hua
• Kuo Hung-Yi
• Tsai Hao-Yi
• Tseng Ming Hung

Classifications

• H10W90/293

  characterised by non-galvanic coupling between the chips, e.g. capacitive coupling · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/9413

  on encapsulations · CPC title