Package structure, fan-out package structure and method of the same

Patent metadata

Field	Value
Publication number	US-10269582-B2
Application number	US-201815861486-A
Country	US
Kind code	B2
Filing date	Jan 3, 2018
Priority date	Oct 14, 2015
Publication date	Apr 23, 2019
Grant date	Apr 23, 2019

Abstract

A package structure includes a spiral coil, a redistribution layer (RDL) and a molding material. The molding material fills gaps of the spiral coil. The spiral coil is connected to the RDL. A fan-out package structure includes a spiral coil, an RDL and a die. The spiral coil has a depth-to-width ratio greater than about 2. The RDL is connected to the spiral coil. The die is coupled to the spiral coil through the RDL. A semiconductor packaging method includes: providing a carrier; adhering a spiral coil on the carrier; adhering a die on the carrier; dispensing a molding material on the carrier to fill gaps between the spiral coil and the die; and disposing a redistribution layer (RDL) over the carrier so as to connect the spiral coil with the die.

First claim

What is claimed is:

1. A semiconductor packaging method, comprising:
providing a carrier;
adhering a spiral coil on the carrier;
adhering a die on the carrier;
dispensing a molding material on the carrier to fill gaps between the spiral coil and the die; and
disposing a redistribution layer (RDL) over the carrier so as to connect the spiral coil with the die.

2. The semiconductor packaging method of claim 1 , wherein the spiral coil is obtained by means of punching, wet etching or laser-cutting.

3. The semiconductor packaging method of claim 1 , wherein the adhering of the spiral coil on the carrier comprises vibrating an alignment pallet carrying the spiral coil and mounting the spiral coil onto the carrier.

4. The semiconductor packaging method of claim 1 , further comprising planarizing the molding material until top ends of the spiral coil and metal pillars of the die are exposed.

5. A semiconductor packaging method, comprising:
providing a carrier;
adhering a first spiral coil including a plurality of coil turns on the carrier;
dispensing a first molding material on the carrier to fill gaps between the coil turns of the first spiral coil; and
planarizing the first molding material until top ends of the coil turns of the first spiral coil are exposed.

6. The semiconductor packaging method of claim 5 , wherein the adhering of the first spiral coil on the carrier comprises vibrating an alignment pallet carrying the first spiral coil and mounting the first spiral coil onto the carrier.

7. The semiconductor packaging method of claim 5 , further comprising forming a contact on the exposed top ends of the coil turns of the first spiral coil.

8. The semiconductor packaging method of claim 7 , further comprising attaching a non-conductive film (NCF) to the planarized first molding material.

9. The semiconductor packaging method of claim 8 , further comprising disposing a second spiral coil including a plurality of coil turns on the NCF, wherein the second spiral coil is coupled to the first spiral coil through the contact.

10. The semiconductor packaging method of claim 9 , further comprising disposing a die of the NCF.

11. The semiconductor packaging method of claim 10 , further comprising dispensing a second molding material on the NCF to fill gaps between the coil turns of the second spiral coil and the die.

12. The semiconductor packaging method of claim 11 , further comprising planarizing the second molding material until top ends of the coil turns of the second spiral coil and metal pillars of the die are exposed.

13. The semiconductor packaging method of claim 12 , further comprising disposing a redistribution layer (RDL) over the carrier so as to couple the second spiral coil with the die.

14. The semiconductor packaging method of claim 13 , further comprising disposing a higher spiral coil at least partially overlapping with the spiral coil.

15. The semiconductor packaging method of claim 13 , further comprising removing the carrier.

16. A semiconductor packaging method, comprising:
providing a carrier;
adhering a spiral coil including a plurality of coil turns on the carrier through an adhesive layer, the coil turns of the spiral coil including a depth-to-width ratio greater than about 2;
dispensing a molding material on the carrier to fill gaps between the coil turns of the spiral coil.

17. The semiconductor packaging method of claim 16 , further comprising planarizing the molding material until top ends of the coil turns of the spiral coil are exposed.

18. The semiconductor packaging method of claim 17 , further comprising forming a redistribution layer (RDL) over the carrier.

19. The semiconductor packaging method of claim 18 , further comprising forming electrical connectors over the RDL.

20. The semiconductor packaging method of claim 19 , further comprising removing the carrier and the adhesive layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hwang Chien Ling
• Liao Hsin-Hung
• Chiu Yu-Ting

Classifications

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/728

  between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors · CPC title

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/07253

  changes in shapes · CPC title