Semiconductor device including a shared semiconductor pattern having faceted sidewalls and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10784379-B2
Application number	US-201815995414-A
Country	US
Kind code	B2
Filing date	Jun 1, 2018
Priority date	Aug 30, 2017
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first fin type pattern on a substrate;
a second fin type pattern on the substrate, the second fin type pattern being parallel to the first fin type pattern;
an epitaxial pattern on the first fin type pattern and the second fin type pattern; and
a capping semiconductor pattern on the epitaxial pattern,
wherein the epitaxial pattern includes a shared semiconductor pattern on the first fin type pattern and the second fin type pattern, the shared semiconductor pattern including
a first sidewall adjacent to the first fin type pattern, and
a second sidewall adjacent to the second fin type pattern,

wherein the first sidewall of the shared semiconductor pattern includes a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower facet and the first upper facet,
wherein the second sidewall of the shared semiconductor pattern includes a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower facet and the second upper facet, and
wherein the capping semiconductor pattern directly covers both an entirety of the first sidewall of the shared semiconductor pattern and an entirety of the second sidewall of the shared semiconductor pattern.

2. The semiconductor device of claim 1 , wherein:
the capping semiconductor pattern includes a first outside wall corresponding to the first sidewall of the shared semiconductor pattern and a second outside wall corresponding to the second sidewall of the shared semiconductor pattern,
the first outside wall of the capping semiconductor pattern includes a third lower facet in parallel with the first lower facet and a third upper facet in parallel with the first upper facet, and
the third lower facet and the third upper facet are directly connected to each other.

3. The semiconductor device of claim 1 , wherein:
the capping semiconductor pattern includes a first outside wall corresponding to the first sidewall of the shared semiconductor pattern and a second outside wall corresponding to the second sidewall of the shared semiconductor pattern,
the first outside wall of the capping semiconductor pattern includes a third lower facet in parallel with the first lower facet, a third upper facet in parallel with the first upper facet, and a third connecting curved surface connecting the third upper facet and the third lower facet, and
a distance between a tip of the first sidewall and a tip of the first outside wall is greater than a distance between the first lower facet and the third lower facet.

4. The semiconductor device of claim 1 , wherein
the capping semiconductor pattern includes a lower capping pattern and an upper capping pattern on the lower capping pattern, and
the lower capping pattern includes a compound semiconductor material, and the upper capping pattern includes an elemental semiconductor material.

5. The semiconductor device of claim 1 , wherein the shared semiconductor pattern includes a compound semiconductor material, and the capping semiconductor pattern includes an elemental semiconductor material.

6. The semiconductor device of claim 1 , wherein:
the epitaxial pattern includes a first lower semiconductor pattern on the first fin type pattern and a second lower semiconductor pattern on the second fin type pattern,
the first lower semiconductor pattern and the second lower semiconductor pattern are spaced apart from each other, and
the shared semiconductor pattern is disposed on the first lower semiconductor pattern and the second lower semiconductor pattern.

7. The semiconductor device of claim 1 , further comprising:
a third fin type pattern, on the substrate, between the first fin type pattern and the second fin type pattern,
wherein the shared semiconductor pattern is extended from the first fin type pattern to the second fin type pattern.

8. The semiconductor device of claim 1 , further comprising:
a field insulating film on the substrate, and
a portion of a sidewall of the first fin type pattern and a portion of a sidewall of the second fin type pattern protrude upward from an upper surface of the field insulating film.

9. The semiconductor device of claim 8 , further comprising a fin spacer along a part of a sidewall of the first fin type pattern on the field insulating film.

10. The semiconductor device of claim 1 , wherein the first and second lower facets and the first and second upper facets are included in a {111} crystal plane group, respectively.

11. The semiconductor device of claim 1 , wherein the shared semiconductor pattern includes silicon germanium.

12. A semiconductor device, comprising:
a first fin type pattern on a substrate;
a second fin type pattern on the substrate and the second fin type pattern in parallel with the first fin type pattern; and
an epitaxial pattern on the first fin type pattern and the second fin type pattern along a first direction,
wherein the epitaxial pattern includes a shared semiconductor pattern and a capping semiconductor pattern on the first fin type pattern and the second fin type pattern, wherein the shared semiconductor pattern includes
a first sidewall adjacent to an outer sidewall of the first fin type pattern,
a second sidewall adjacent to an outer sidewall of the second fin type pattern,
an upper surface connecting the first sidewall and the second sidewall; and
a bottom surface extending between an inner sidewall of the first fin type pattern and to an inner sidewall of the second fin type pattern, wherein a height from a lowest portion of the bottom surface to a highest portion of the bottom surface along the first direction is smaller than a height from the highest portion of the bottom surface to the upper surface overlapping the highest portion of the bottom surface,
wherein the first sidewall of the shared semiconductor pattern includes a first lower facet, a first upper facet on the first lower facet, and a first connecting curved surface connecting the first lower facet and the first upper facet,
wherein the second sidewall of the shared semiconductor pattern includes a second lower facet, a second upper facet on the second lower facet, and a second connecting curved surface connecting the second lower facet and the second upper facet, and

wherein the capping semiconductor pattern extends along the first sidewall and the second sidewall of the shared semiconductor pattern.

13. The semiconductor device of claim 12 , wherein:
a width of a portion of the capping semiconductor pattern increases along the first and second lower facets and decreases along the first and second upper facets as a distance from the substrate increases.

14. The semiconductor device of claim 13 , wherein
a first outside wall of the capping semiconductor pattern includes a third lower facet in parallel with the first lower facet, and a third upper facet in parallel with the first upper facet, and
a distance from a tip of the first sidewall to a tip of the first outside wall is greater than a distance between the first lower facet and the third lower facet.

15. The semiconductor device of claim 14 , wherein the third lower facet and the third upper facet are directly connected to each other.

16. The semiconductor device of claim 12 , wherein the shared semiconductor pattern includes a compound semiconductor material, and the capping semiconductor pattern includes an elemental semiconductor material.

17. A semiconductor device, comprising:
a

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Seok Hoon
• Kim Dong Myoung
• Shin Dong Suk
• Lee Seung Hun
• Lee Cho Eun
• Lee Hyun Jung
• Jang Sung Uk
• Cho Edward Nam Kyu
• Choi Min-Hee

Classifications

• H10P14/274

  using seed materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W20/042

  the barrier, adhesion or liner layers being seed or nucleation layers · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title