Semiconductor devices including active fins and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016293697-A1
Application number	US-201615058466-A
Country	US
Kind code	A1
Filing date	Mar 2, 2016
Priority date	Mar 30, 2015
Publication date	Oct 6, 2016
Grant date	—

Abstract

Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.

First claim

1 . A semiconductor device, comprising:
a plurality of active fins each extending in a first direction on a substrate; a gate structure on the plurality of active fins, the gate structure extending in a second direction that is different from the first direction; and a first source/drain layer on the plurality of active fins and adjacent a side of the gate structure, wherein at least one of opposing sidewalls of a cross-section of the first source/drain layer that is taken along the second direction includes a first curved portion having a slope with respect to an upper surface of the substrate, and an absolute value of the slope of the first curved portion decreases from a bottom of the first curved portion that is close to the substrate to a top thereof.

2 . The semiconductor device of claim 1 , wherein the cross-section of the first source/drain layer includes:
an upper surface including first and second linear portions having first and second slopes, respectively, with respect to the upper surface of the substrate; a lower surface including third and fourth linear portions having the first and second slopes, respectively, with respect to the upper surface of the substrate; and the sidewalls each connecting the upper surface and the lower surface.

3 . The semiconductor device of claim 2 , wherein the lower surface of the cross-section of the first source/drain layer further includes a fifth linear portion connecting one of the third linear portions to one of the fourth linear portions and having a zero degree slope with respect to the upper surface of the substrate.

4 . The semiconductor device of claim 1 , wherein the plurality of active fins include two first active fins, and
wherein the cross-section of the first source/drain layer includes:
an upper surface including two first linear portions each having a first slope with respect to the upper surface of the substrate and two second linear portions each having a second slope with respect to the upper surface of the substrate; and
a lower surface including two third linear portions each having the first slope with respect to the upper surface of the substrate, two fourth linear portions each having the second slope with respect to the upper surface of the substrate, and two fifth linear portions each connecting one of the third linear portions to one of the fourth linear portions, wherein a first sidewall of the sidewalls of the cross-section of the first source/drain layer connects one of the first linear portions of the upper surface and one of the fourth linear portions of the lower surface, and a second sidewall of the sidewalls connects one of the second linear portions of the upper surface and one of the third linear portions of the lower surface.

5 . The semiconductor device of claim 1 , wherein the opposing sidewalls of the cross-section of the first source/drain layer are symmetrical with respect to an imaginary line passing a center of the first source/drain layer and extending in a vertical direction that is substantially perpendicular to the upper surface of the substrate.

6 . The semiconductor device of claim 1 , wherein the plurality of active fins include a plurality of first active fins in a first region of the substrate and a plurality of second active fins in a second region of the substrate, and the second region is spaced apart from the first region in the second direction,
wherein the semiconductor device further comprises a second source/drain layer, at least one of opposing sidewalls of a cross-section of the second source/drain layer that is taken along the second direction includes a second curved portion having a slope with respect to the upper surface of the substrate, and an absolute value of the slope of the second curved portion decreases from a bottom of the second curved portion that is close to the substrate to a top thereof, and wherein the first and second source/drain layers are spaced apart from each other in the second direction.

7 . The semiconductor device of claim 6 , wherein a distance between ones of the plurality of first active fins and a distance between ones of the plurality of second active fins are less than a distance between the plurality of first active fins and the plurality of second active fins

8 . The semiconductor device of claim 1 , wherein the first source/drain layer includes silicon-germanium, silicon and/or silicon carbide.

9 . The semiconductor device of claim 1 , wherein the gate structure includes an interface pattern, a gate insulation pattern and a gate electrode sequentially stacked on the plurality of active fins.

10 . The semiconductor device of claim 9 , wherein the interface pattern, the gate insulation pattern and the gate electrode include silicon oxide, a metal oxide having a dielectric constant higher than silicon oxide, and a metal, respectively.

11 . The semiconductor device of claim 1 , further comprising gate spacers on respective opposing sidewalls of the gate structure that are spaced apart from each other in the first direction, wherein the first source/drain layer contacts an outer sidewall of one of the gate spacers.

12 . A semiconductor device, comprising:
an active fin on a substrate; a gate structure on the active fin; and a source/drain layer on the active fin and adjacent a side of the gate structure, wherein at least one of opposing sidewalls of a cross-section of the source/drain layer includes a curved portion having a slope with respect to an upper surface of the substrate, and an absolute value of the slope of the curved portion decreases from a bottom of the curved portion that is close to the substrate to a top thereof.

13 . The semiconductor device of claim 12 , wherein the substrate includes first and second regions,
wherein the active fin includes a plurality of first active fins in the first region and a plurality of second active fins in the second region, and wherein the source/drain layer includes a first source/drain layer on the plurality of first active fins and a second source/drain layer on the plurality of second active fins.

14 . The semiconductor device of claim 13 , wherein each of the plurality of first active fins and the plurality of second active fins extends in a first direction, and the plurality of first active fins and the plurality of second active fins are arranged in a second direction that is different from the first direction,
wherein the first and second regions are spaced apart from each other in the second direction, and wherein the cross-section of the source/drain layer is taken along the second direction.

15 . The semiconductor device of claim 14 , wherein a distance between ones of the plurality of first active fins and a distance between ones of the plurality of second active fins are less than a distance between the plurality of first active fins and the plurality of second active fins, and
wherein the first and second source/drain layers are spaced apart from each other in the second direction.

16 . A semiconductor device, comprising:
a plurality of active fins each extending in a first direction on a substrate; a gate structure on the plurality of active fins, the gate structure extending in a second direction that is different from the first direction; gate spacers on respective sidewalls of the gate structure opposed to each other in the first direction; and a first source/drain layer on the plurality of active fins and adjacent the sidewall of the gate structure, wherein an upper surface of the first source/drain layer is higher than lower surfaces of the gate

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dong-Woo
• Maeda Shigenobu
• Choi Young-Moon
• Kwon Yong-Bum
• Sohn Chang-Woo
• Lee Do-Sun

Classifications

• H10D30/0245

  by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/834 Primary

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title