Method of making a semiconductor component having through-silicon vias

Patent metadata

Field	Value
Publication number	US-10784162-B2
Application number	US-201816168306-A
Country	US
Kind code	B2
Filing date	Oct 23, 2018
Priority date	Apr 13, 2011
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress. The method further includes depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress. The method further includes depositing a conductive material over the second dielectric liner.

First claim

What is claimed:

1. A method of making a semiconductor component comprising:
etching a substrate to define an opening;
depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress;
depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress; and
depositing a conductive material over the second dielectric liner.

2. The method of claim 1 , wherein the depositing the first dielectric liner comprises depositing the first dielectric liner having a first thickness ratio, the first thickness ratio is determined based on a thickness of the first dielectric liner at a top portion of the opening and a thickness of the first dielectric liner at a bottom portion of the opening.

3. The method of claim 2 , wherein the depositing the first dielectric liner comprises depositing the second dielectric liner having a second thickness ratio, the second thickness ratio is determined based on a thickness of the second dielectric liner at the top portion of the opening and a thickness of second the dielectric liner at the bottom portion of the opening, and the first thickness ratio is different from the second thickness ratio.

4. The method of claim 1 , wherein the depositing the first dielectric liner comprises depositing the first dielectric liner having a first etching rate in a HF solution.

5. The method of claim 4 , wherein the depositing the second dielectric liner comprises depositing the second dielectric liner having a second etching rate in a HF solution, and the second etching rate is different from the first etching rate.

6. The method of claim 1 , further comprising planarizing the substrate to expose the conductive material at a top surface and a bottom surface of the planarized substrate.

7. The method of claim 1 , further comprising depositing a metal barrier layer over the second dielectric liner, wherein the depositing the conductive material comprises depositing the conductive material over the metal barrier layer.

8. A method of making a semiconductor component comprising:
etching a substrate to define an opening;
depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first thickness ratio, the first thickness ratio is determined based on a thickness of the first dielectric liner at a top portion of the opening and a thickness of the first dielectric liner at a bottom portion of the opening, and the depositing the first dielectric liner comprises depositing the first dielectric liner having a first stress;
depositing a second dielectric liner on the first dielectric liner, wherein the second dielectric liner has a second thickness ratio, the second thickness ratio is determined based on a thickness of the second dielectric liner at the top portion of the opening and a thickness of second the dielectric liner at the bottom portion of the opening, and the depositing the second dielectric liner comprises depositing the second dielectric liner having a second stress, and a direction of the first stress is opposite a direction of the second stress; and
depositing a conductive material of the second dielectric layer.

9. The method of claim 8 , wherein the first thickness ratio is greater than about 5.

10. The method of claim 9 , wherein the second thickness ratio is less than or equal to about 5.

11. The method of claim 10 , wherein the depositing the second dielectric liner comprises depositing the second dielectric liner having a magnitude of the second stress different from a magnitude of the first stress.

12. The method of claim 8 , wherein the depositing the first dielectric liner comprises depositing the first dielectric liner having a first etching rate in a HF solution.

13. The method of claim 12 , wherein the depositing the second dielectric liner comprises depositing the second dielectric liner having a second etching rate in a HF solution, and the second etching rate is different from the first etching rate.

14. A method of making a semiconductor component comprising:
etching a substrate to define an opening;
depositing a first dielectric liner in the opening, wherein the first dielectric liner has a thickness of the first dielectric liner at a top portion of the opening different from a thickness of the first dielectric liner at a bottom portion of the opening, and the first dielectric liner has a first etching rate in a HF solution;
depositing a second dielectric liner on the first dielectric liner, wherein the second dielectric liner has a second etching rate in a HF solution, and the second etching rate is different from the first etching rate; and
depositing a conductive material of the second dielectric layer.

15. The method of claim 14 , wherein the depositing the first dielectric liner comprises depositing the first dielectric liner having a first stress.

16. The method of claim 15 , wherein the depositing the second dielectric liner comprises depositing the second dielectric liner having a second stress, and a direction of the first stress is opposite a direction of the second stress.

17. The method of claim 14 , wherein the depositing the first dielectric liner comprises depositing the first dielectric liner having a first thickness ratio, the first thickness ratio is determined based on a thickness of the first dielectric liner at a top portion of the opening and a thickness of the first dielectric liner at a bottom portion of the opening.

18. The method of claim 17 , wherein the depositing the first dielectric liner comprises depositing the second dielectric liner having a second thickness ratio, the second thickness ratio is determined based on a thickness of the second dielectric liner at the top portion of the opening and a thickness of second the dielectric liner at the bottom portion of the opening, and the first thickness ratio is different from the second thickness ratio.

19. The method of claim 14 , wherein the depositing the first dielectric liner comprises depositing the first dielectric liner using plasma enhanced chemical vapor deposition (PECVD).

20. The method of claim 14 , wherein the depositing the second dielectric liner comprises depositing the second dielectric liner using a high aspect ratio process (HARP).

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Chang Cheng-Hung
• Liao Ebin
• Yu Chia-Lin
• Wang Hsiang-Yi
• Chang Chun Hua
• Huang Li-Hsien
• Kuo Darryl
• Wu Tsang-Jiuh
• Chiou Wen-Chih

Classifications

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P52/402

  of semiconductor materials · CPC title