Using materials with different etch rates to fill trenches in semiconductor devices

Patent metadata

Field	Value
Publication number	US-9704798-B2
Application number	US-201314137497-A
Country	US
Kind code	B2
Filing date	Dec 20, 2013
Priority date	Dec 20, 2013
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

An embodiment includes a metal interconnect structure, comprising: a dielectric layer on a substrate; an opening in the dielectric layer, wherein the opening has opening sidewalls and exposes a conductive region of at least one of the substrate and an additional interconnect structure; a first atomic layer deposition (ALD) layer on the conductive region and the opening sidewalls; a second ALD layer on a portion of the first ALD layer, and a third ALD layer within the opening and on the first ALD layer. Other embodiments are described herein.

First claim

What is claimed is:

1. A metal interconnect structure, comprising:
a dielectric layer on a substrate;
an opening in the dielectric layer, wherein the opening has opening sidewalls and exposes a conductive region of at least one of the substrate and an additional interconnect structure;
a first conformal thin film layer (first layer) on the conductive region and the opening sidewalls;
a second conformal thin film layer (second layer) within the opening and on a portion of the first layer, and
a third conformal thin film layer (third layer) within the opening and on the first layer;
wherein (a) the third layer directly contacts the first and second layers, (b) the opening sidewalls continuously taper inward along each of a bottom, a middle, and a top of the opening so that the opening is narrower at its top than at its bottom, and (c) a horizontal axis, parallel to the substrate, intersects a second layer sidewall portion that tapers outward and an opening sidewall portion that tapers inward.

2. The structure of claim 1 , wherein the first and second layers include different material compositions.

3. The structure of claim 1 , wherein:
the first layer includes a first material having a first etch rate; and
the second layer includes a second material having a second etch rate that is faster than the first etch rate.

4. The structure of claim 3 , wherein the first and third layers include equivalent material compositions.

5. The structure of claim 3 , wherein each of the first, second, and third layers is formed using at least one of atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, electroless plating, and e-beam evaporation.

6. The structure of claim 5 , wherein the first layer is more thickly formed near the bottom of the opening than near the top of the opening.

7. The structure of claim 6 , wherein the second layer is more thickly formed near the bottom of the opening than near the top of the opening.

8. The structure of claim 1 , wherein the opening has (a) an opening height from a top of the opening to a bottom of the opening and an opening width at the bottom of the opening, and (b) an aspect ratio (the opening height:the opening width) of at least 1.7.

9. The structure of claim 3 , wherein:
the first material is selected from the group comprising silicon oxide, silicon nitride, silicon oxyfluoride, silicon oxynitride, tantalum, tantalum nitride, titanium, and titanium nitride;
the second material, including a different chemical element from the first material, is selected from the group comprising silicon oxide, silicon nitride, silicon oxyfluoride, silicon oxynitride, tantalum, tantalum nitride, titanium, titanium nitride, aluminum, and copper; and
the third layer includes a third material selected from the group comprising silicon oxide, silicon nitride, silicon oxyfluoride, silicon oxynitride, a tantalum, tantalum nitride, titanium, titanium nitride, aluminum, and copper.

10. The structure of claim 1 , wherein at least one of (a) the first layer forms first layer sidewalls that taper inwards towards the bottom of the opening, and (b) the second layer forms second layer sidewalls that taper inwards towards the bottom of the opening.

11. The structure of claim 1 , wherein the first and second layers are collectively no thicker than 50% of a minimum width of the opening.

12. The structure of claim 1 , wherein the first layer directly contacts the conductive region and the dielectric layer.

13. The structure of claim 1 , wherein the opening having opening sidewalls and exposing the conductive region of at least one of the substrate and the additional interconnect structure comprises the opening sidewalls directly contacting the conductive region and the opening including no bottom wall to separate the conductive region from the opening.

14. The structure of claim 12 , wherein the third layer directly contacts the conductive region of the substrate.

15. The structure of claim 1 , wherein the first layer directly contacts the conductive region of the substrate.

16. The structure of claim 1 , wherein a middle portion of each of the opening sidewalls directly contacts the dielectric layer.

17. The structure of claim 16 , wherein the opening directly interfaces the conductive region of the substrate.

18. An semiconductor structure, comprising:
a dielectric layer on a substrate;
an opening in the dielectric layer, wherein the opening has opening sidewalls;
a first conformal deposition layer (first layer) on the opening sidewalls;
a second conformal deposition layer (second layer) on a portion of the first layer, and
a third conformal deposition layer (third layer) within the opening and directly contacting the first and second layers;
wherein a horizontal axis, which is parallel to the substrate, intersects (a) a portion of the opening sidewalls that taper inward moving away from the substrate, and (b) a portion of second layer sidewalls that taper outward moving away from the substrate.

19. The structure of claim 18 wherein the first layer includes at least one of an atomic layer deposition (ALD) layer, chemical vapor deposition (CVD) layer, physical vapor deposition (PVD) layer, electroplated layer, electroless plated layer, and e-beam evaporation layer and the semiconductor structure includes at least one of a metal interconnect, a transistor gate, and a trench contact.

20. The structure of claim 19 , wherein:
the first layer includes a first material having a first etch rate; and
the second layer includes a second material having a second etch rate that is faster than the first etch rate.

21. A semiconductor structure, comprising:
a dielectric layer on a substrate;
an opening in the dielectric layer, wherein the opening has opening sidewalls;
a first conformal deposition layer (first layer) on the opening sidewalls;
a second conformal deposition layer (second layer) on a portion of the first layer, and
a third conformal deposition layer (third layer): (a)(i) within the opening, (a)(ii) directly contacting the first layer at a location within the opening, and (a)(iii) directly contacting the second layer at another location within the opening;
wherein the first layer: (b)(i) directly contacts a conductive region and the dielectric layer, and (b)(ii) is an etch stop layer.

22. The structure of claim 21 wherein:
the first layer includes at least one of an atomic layer deposition (ALD) layer, chemical vapor deposition (CVD) layer, physical vapor deposition (PVD) layer, electroplated layer, electroless plated layer, and e-beam evaporation layer;
the first layer includes a first material selected from the group comprising silicon oxide, silicon nitride, silicon oxyfluoride, silicon oxynitride; and
the semiconductor structure includes at least one of a metal interconnect, a transistor gate, and a trench contact.

23. The structure of claim 22 , wherein the opening sidewalls taper inwards near a top of the opening and at least one of (a) the first layer forms first layer sidewalls that taper inwards towards a bottom of the opening, and (b) the second layer forms second layer sidewalls that taper inwards towards the bottom of the opening.

24. The structure of claim 22 , wherein the opening is narrower at its top than at its bottom.

25. The structure of claim 23 , wherein:
the first layer includes a first material having a f

Assignees

• Intel Corp

Inventors

• Govindaraju Sridhar
• Dasgupta Anindya
• Grover Rohit

Classifications

• H10W20/0595

  by using multiple deposition steps separated by etching steps · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title