Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress

Patent metadata

Field	Value
Publication number	US-10784146-B2
Application number	US-201916720136-A
Country	US
Kind code	B2
Filing date	Dec 19, 2019
Priority date	Mar 3, 2015
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow.

First claim

What is claimed is:

1. A multilayer structure comprising:
a single crystal semiconductor handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm;
a textured semiconductor oxide layer, a textured semiconductor nitride layer, or a textured semiconductor oxynitride layer in interfacial contact with the front surface of the single crystal semiconductor handle substrate, wherein the textured semiconductor oxide layer comprises holes having sizes between about 5 nanometers and about 1000 nanometers, the textured semiconductor nitride layer comprises holes having sizes between about 5 nanometers and about 1000 nanometers, or the textured semiconductor oxynitride layer comprises holes having sizes between about 5 nanometers and about 1000 nanometers;
a polycrystalline silicon layer in interfacial contact with the textured semiconductor oxide layer, the textured semiconductor nitride layer, or the textured semiconductor oxynitride layer;
a dielectric layer in interfacial contact with the polycrystalline silicon layer; and
a single crystal semiconductor device layer in interfacial contact with the dielectric layer,
wherein the multilayer structure has wafer bow as measured by at least three points on a front surface of the semiconductor device layer and/or the back surface of the single crystal semiconductor handle substrate of less than about 80 micrometers.

2. The multilayer structure of claim 1 wherein the single crystal semiconductor handle substrate comprises a single crystal silicon wafer, and the textured semiconductor oxide layer comprises textured silicon dioxide.

3. The multilayer structure of claim 1 wherein the single crystal semiconductor handle substrate comprises a single crystal silicon wafer, and the textured semiconductor nitride layer comprises textured silicon nitride.

4. The multilayer structure of claim 1 wherein the single crystal semiconductor handle substrate comprises a single crystal silicon wafer, and the textured semiconductor oxynitride layer comprises textured silicon oxynitride.

5. The multilayer structure of claim 1 wherein the holes have sizes between about 5 nanometers and about 500 nanometers.

6. The multilayer structure of claim 1 wherein the holes have sizes between about 5 nanometers and about 200 nanometers.

7. The multilayer structure of claim 1 wherein the textured semiconductor oxide layer, the textured semiconductor nitride layer, or the textured semiconductor oxynitride layer has a thickness between about 0.1 nanometers and about 25 nanometers.

8. The multilayer structure of claim 1 wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 500 Ohm-cm and about 100,000 Ohm-cm.

9. The multilayer structure of claim 1 wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 1000 ohm cm and about 10,000 Ohm-cm.

10. The multilayer structure of claim 1 wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 3000 Ohm cm and about 5,000 Ohm-cm.

11. The multilayer structure of claim 1 wherein the polycrystalline silicon layer has a thickness between about 0.1 micrometer and about 10 micrometers.

12. The multilayer structure of claim 1 wherein the polycrystalline silicon layer has a thickness between about 0.5 micrometer and about 5 micrometers.

13. The multilayer structure of claim 1 wherein the polycrystalline silicon layer has a resistivity of at least about 1000 Ohm-cm.

14. The multilayer structure of claim 1 wherein the polycrystalline silicon layer has a resistivity of at least about 3000 Ohm-cm.

15. The multilayer structure of claim 1 wherein the wafer bow as measured by at least three points on the front surface of the semiconductor device layer and/or the back surface of the single crystal semiconductor handle substrate of less than about 60 micrometers.

16. The multilayer structure of claim 1 wherein the wafer bow as measured by at least three points on the front surface of the semiconductor device layer and/or the back surface of the single crystal semiconductor handle substrate of less than about 20 micrometers.

Assignees

• Globalwafers Co Ltd

Inventors

• Wang Gang
• Libbert Jeffrey L
• Thomas Shawn George
• Peidous Igor

Classifications

• H10P90/1914

  using bonding · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3256

  Microstructure · CPC title

• H10P14/3238

  being insulating materials · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title