Slit stress modulation in semiconductor substrates

Patent metadata

Field	Value
Publication number	US-10784144-B2
Application number	US-201815897935-A
Country	US
Kind code	B2
Filing date	Feb 15, 2018
Priority date	Feb 29, 2016
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

A disclosed example to modulate slit stress in a semiconductor substrate includes a first controller to, after obtaining a wafer stress measurement of the semiconductor substrate, control a first process to apply a first material to the semiconductor substrate based on the wafer stress measurement, the semiconductor substrate including a slit between adjacent stacked transistor layers, the first material coating walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width; and a second controller to control a second process to apply a second material to the semiconductor substrate, the second material to be deposited in the second width of the slit, the first material and the second material to form a solid structure in the slit between the adjacent stacked transistor layers.

First claim

What is claimed is:

1. An apparatus to modulate slit stress in a semiconductor substrate, the apparatus comprising:
a first controller to, after obtaining a wafer stress measurement of the semiconductor substrate, control application of a first material to the semiconductor substrate based on the wafer stress measurement to coat walls of a slit between adjacent stacked transistor layers of the semiconductor substrate to reduce a first width of the slit to a second width; and
a second controller to control application of a second material to the semiconductor substrate to deposit the second material in the second width of the slit to form a solid structure by the first material and the second material in the slit between the adjacent stacked transistor layers.

2. An apparatus of claim 1 , wherein the first controller is to control a thickness of the first material based on a material thickness parameter.

3. An apparatus of claim 2 , further including a fill parameter value generator to select a value for the material thickness parameter to modulate at least one of global stress across the semiconductor substrate or local stress surrounding the slit between the adjacent stacked transistor layers.

4. An apparatus of claim 3 , further including a stress monitor to monitor the at least one of the global stress or the local stress, the fill parameter value generator to select the value for the material thickness parameter when the at least one of the global stress or the local stress satisfy at least one of a threshold global stress or a threshold local stress.

5. An apparatus of claim 2 , further including a fill parameter value generator to select a value for the material thickness parameter to prevent the first material from forming a pinch-off structure in the slit.

6. An apparatus of claim 1 , wherein the first controller is to control the application of the first material without forming a pinch-off structure in the slit with the first material.

7. An apparatus of claim 1 , wherein the second controller is to control the application of the second material based on a densification temperature parameter to set a temperature used to densify the second material.

8. An apparatus of claim 1 , wherein the second controller is to control the application of the second material based on a densification time parameter to control a duration of a densification phase to densify the second material.

9. An apparatus of claim 1 , wherein the first controller is to control the application of the first material by a chemical vapor deposition (CVD) high aspect ratio process (HARP), and the second controller is to control the application of the second material by a spin-on-dielectric (SOD) process.

10. An apparatus of claim 1 , wherein the adjacent stacked transistor layers are configured in a three dimensional (3D) stacked configuration.

11. An apparatus of claim 1 , wherein the first controller and the second controller are implemented using one processor.

12. An apparatus to modulate slit stress in a semiconductor substrate, the apparatus comprising:
first means for controlling to, after obtaining a wafer stress measurement of the semiconductor substrate, control application of a first material to the semiconductor substrate based on the wafer stress measurement to coat walls of a slit between adjacent stacked transistor layers of the semiconductor substrate to reduce a first width of the slit to a second width; and
second means for controlling application of a second material to the semiconductor substrate to deposit the second material in the second width of the slit to form a solid structure by the first material and the second material in the slit between the adjacent stacked transistor layers.

13. An apparatus of claim 12 , wherein the first means for controlling is to control a thickness of the first material by depositing the first material based on a material thickness parameter.

14. An apparatus of claim 13 , further including means for selecting a value for the material thickness parameter to modulate at least one of global stress across the semiconductor substrate or local stress surrounding the slit between the adjacent stacked transistor layers.

15. An apparatus of claim 14 , further including means for monitoring the at least one of the global stress or the local stress, the means for selecting the value for the material thickness parameter to select the value for the material thickness parameter when the at least one of the global stress or the local stress satisfy at least one of a threshold global stress or a threshold local stress.

16. An apparatus of claim 13 , further including means for selecting a value for the material thickness parameter to prevent the first material from forming a pinch-off structure in the slit.

17. An apparatus of claim 12 , wherein the first means for controlling is to control the application of the first material without forming a pinch-off structure in the slit with the first material.

18. An apparatus of claim 12 , wherein the second means for controlling is to use a densification temperature parameter to set a temperature used to densify the second material.

19. An apparatus of claim 12 , wherein the second means for controlling is to use a densification time parameter to control a duration of a densification phase to densify the second material.

20. An apparatus of claim 12 , wherein the first means for controlling is to control the application of the first material by a chemical vapor deposition (CVD) high aspect ratio process (HARP), and the second means for controlling is to control the application of the second material by a spin-on-dielectric (SOD) process.

21. An apparatus of claim 12 , wherein the adjacent stacked transistor layers are configured in a three dimensional (3D) stacked configuration.

Assignees

• Intel Corp

Inventors

• Mathew James
• Ho Yunjun
• Xie Zhiqiang
• Kim Hyun Sik

Classifications

• H10P74/238

  comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement · CPC title

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P14/6342

  Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title