Slit stress modulation in semiconductor substrates

Patent metadata

Field	Value
Publication number	US-9935000-B2
Application number	US-201615056620-A
Country	US
Kind code	B2
Filing date	Feb 29, 2016
Priority date	Feb 29, 2016
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

A disclosed example to modulate slit stress in a semiconductor substrate includes controlling a first process to apply a first material to a semiconductor substrate. The semiconductor substrate includes a slit between adjacent stacked transistor layers. The first material coats walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width. A second process is controlled to apply a second material to the semiconductor substrate. The second material is to be deposited in the second width of the slit. The first material and the second material are to form a solid structure in the slit between the adjacent stacked transistor layers.

First claim

What is claimed is:

1. A method to modulate slit stress in a semiconductor substrate, the method comprising:
after obtaining a wafer stress measurement of the semiconductor substrate, controlling a first process to apply a first material to the semiconductor substrate based on the wafer stress measurement, the semiconductor substrate including a slit between adjacent stacked transistor layers, the first material coating walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width; and
controlling a second process to apply a second material to the semiconductor substrate, the second material to be deposited in the second width of the slit, the first material and the second material to form a solid structure in the slit between the adjacent stacked transistor layers.

2. A method of claim 1 , further including controlling a thickness of the first material by depositing the first material based on a material thickness parameter.

3. A method of claim 2 , further including selecting a value for the material thickness parameter to modulate at least one of global stress across the semiconductor substrate or local stress surrounding the slit between the adjacent stacked transistor layers.

4. A method of claim 2 , further including selecting a value for the material thickness parameter to prevent the first material from forming a pinch-off structure in the slit.

5. A method of claim 1 , further including controlling the first process to apply the first material without forming a pinch-off structure in the slit with the first material.

6. A method of claim 1 , further including controlling the second process based on a densification temperature parameter to set a temperature used to densify the second material.

7. A method of claim 1 , further including controlling the second process based on a densification time parameter to control a duration of a densification phase to densify the second material.

8. A method of claim 1 , wherein the first process is a chemical vapor deposition (CVD) high aspect ratio process (HARP), and the second process is a spin-on-dielectric (SOD) process.

9. A method of claim 1 , wherein the adjacent stacked transistor layers are configured in a three dimensional (3D) stacked configuration.

10. A method of claim 1 , further including controlling the first process to change a wafer stress of the semiconductor substrate based on the applying of the first material.

11. At least one article of manufacture comprising machine readable instructions that, when executed, cause a processor to at least:
after obtaining a wafer stress measurement of a semiconductor substrate, control a first process to apply a first material to the semiconductor substrate based on the wafer stress measurement, the semiconductor substrate including a slit between adjacent stacked transistor layers, the first material coating walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width; and
control a second process to apply a second material to the semiconductor substrate, the second material to be deposited in the second width of the slit, the first material and the second material to form a solid structure in the slit between the adjacent stacked transistor layers.

12. At least one article of manufacture of claim 11 , further including instructions to cause the processor to control the first process by controlling a thickness of the first material by depositing the first material based on a material thickness parameter.

13. At least one article of manufacture of claim 12 , further including instructions to cause the processor to select a value for the material thickness parameter to modulate at least one of global stress across the semiconductor substrate or local stress surrounding the slit between the adjacent stacked transistor layers.

14. At least one article of manufacture of claim 12 , further including instructions to cause the processor to select a value for the material thickness parameter to prevent the first material from forming a pinch-off structure in the slit.

15. At least one article of manufacture of claim 11 , further including instructions to cause the processor to control the first process to apply the first material without forming a pinch-off structure in the slit with the first material.

16. At least one article of manufacture of claim 11 , further including instructions to cause the processor to control the second process based on a densification temperature parameter to set a temperature used to densify the second material.

17. At least one article of manufacture of claim 11 , further including instructions to cause the processor to control the second process based on a densification time parameter to control a duration of a densification phase to densify the second material.

18. At least one article of manufacture of claim 11 , wherein the first process is a chemical vapor deposition (CVD) high aspect ratio process (HARP), and the second process is a spin-on-dielectric (SOD) process.

19. At least one article of manufacture of claim 11 , wherein the adjacent stacked transistor layers are configured in a three dimensional (3D) stacked configuration.

20. At least one article of manufacture of claim 11 , further including instructions to cause the processor to control the first process to change a wafer stress of the semiconductor substrate based on the applying of the first material to the semiconductor substrate.

21. An integrated circuit die comprising:
first and second stacked transistor layer structures;
a slit structure having a high aspect ratio, the slit structure interposing the first and second stacked transistor layer structures;
a first fill material structured on first sidewalls of the slit structure, the first fill material structured to have a thickness selected based on a previous wafer stress measurement associated with the first and second stacked transistor layer structures, the thickness to create a wafer stress in the integrated circuit die that satisfies a target stress value; and
a second fill material applied to second sidewalls created by the first fill material in the slit structure.

22. An integrated circuit die of claim 21 , wherein the first fill material reduces the width of the slit structure from a first width to a narrower, second width defined by the second sidewalls.

23. An integrated circuit die of claim 21 , wherein the first fill material and the second fill material create a solid electrically insulating structure in the slit structure.

24. An integrated circuit die of claim 23 , wherein the solid electrically insulating structure fills the slit structure without air gaps in the slit structure.

25. An integrated circuit die of claim 21 , wherein the first fill material is a high aspect ratio process (HARP) fill material, and the second fill material is a spin-on-dielectric (SOD) fill material.

26. An integrated circuit die of claim 21 , wherein the first and second stacked transistor layer structures, the slit structure, and the first and second fill materials are located in a chip package.

27. An integrated circuit die of claim 21 , wherein the stacked transistor layer structures form 3D NAND flash memory cells.

28. An integrated circuit die of claim 21 , including one or more of:
one or more process

Assignees

• Intel Corp

Inventors

• Mathew James
• Ho Yunjun
• Xie Zhiqiang
• Kim Hyun Sik

Classifications

• H10P74/238

  comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement · CPC title

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P14/6342

  Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title