Stress tuning for reducing wafer warpage

Patent metadata

Field	Value
Publication number	US-9484303-B2
Application number	US-201313946728-A
Country	US
Kind code	B2
Filing date	Jul 19, 2013
Priority date	Mar 13, 2013
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

An integrated circuit structure includes a substrate, a plurality of low-k dielectric layers over the substrate, a first dielectric layer over the plurality of low-k dielectric layers, and a metal line in the first dielectric layer. A stress tuning dielectric layer is over the first dielectric layer, wherein the stress tuning dielectric layer includes a first opening and a second opening. The metal line extends into the first opening. The second opening has a bottom substantially level with a top surface of the first dielectric layer. A second dielectric layer is over the first dielectric layer.

First claim

What is claimed is:

1. An integrated circuit structure comprising:
a substrate;
a plurality of low-k dielectric layers over the substrate;
a first dielectric layer over the plurality of low-k dielectric layers;
a metal line in the first dielectric layer;
a stress tuning dielectric layer over the first dielectric layer, wherein the stress tuning dielectric layer comprises:
a first opening, wherein the metal line extends into the first opening; and
a second opening with a bottom substantially level with a top surface of the first dielectric layer; and

a second dielectric layer over the first dielectric layer.

2. The integrated circuit structure of claim 1 , wherein the first dielectric layer comprises un-doped silicate glass.

3. The integrated circuit structure of claim 1 , wherein the second dielectric layer extends into the second opening to contact the first dielectric layer.

4. The integrated circuit structure of claim 1 , wherein the second opening is in a semiconductor chip, and wherein the second opening forms a ring comprising four sides, with each of the four sides adjacent to one of four edges of the semiconductor chip.

5. The integrated circuit structure of claim 4 , wherein the stress tuning dielectric layer further comprises a plurality of openings isolated from each other and disconnected from any metallic feature, and wherein the second dielectric layer extends into the plurality of openings to contact the first dielectric layer.

6. The integrated circuit structure of claim 1 further comprising:
an etch stop layer over the stress tuning dielectric layer, wherein the etch stop layer penetrates through the second opening to contact the first dielectric layer; and
an un-doped silicate glass layer over and contacting the etch stop layer.

7. The integrated circuit structure of claim 1 further comprising:
a passivation layer over the stress tuning dielectric layer, wherein the passivation layer penetrates through the second opening to contact the first dielectric layer, and wherein the passivation layer comprises an oxide layer and a nitride layer over and contacting the oxide layer; and
an aluminum-containing pad over the stress tuning dielectric layer, wherein the aluminum-containing pad is electrically coupled to the metal line.

8. An integrated circuit structure comprising:
a substrate;
a plurality of low-k dielectric layers over the substrate;
a first dielectric layer over the plurality of low-k dielectric layers;
a via in the first dielectric layer;
a second dielectric layer over the first dielectric layer;
a metal line in the second dielectric layer and forming an integrated metal feature with the via; and
a stress tuning region continuously extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer, wherein the stress tuning region comprises a dielectric material or a metal feature that is electrically floating.

9. The integrated circuit structure of claim 8 , wherein the stress tuning region is formed of a dielectric material different from dielectric materials of the first dielectric layer and the second dielectric layer.

10. The integrated circuit structure of claim 8 , wherein the stress tuning region is formed of a dielectric material with a lower inner stress than the first dielectric layer and the second dielectric layer.

11. The integrated circuit structure of claim 8 , wherein the stress tuning region comprises a metal.

12. The integrated circuit structure of claim 8 , wherein the stress tuning region comprises a straight edge continuously extends from the top surface of the second dielectric layer to the bottom surface of the first dielectric layer.

13. The integrated circuit structure of claim 8 , wherein the first dielectric layer and the second dielectric layer comprise un-doped silicate glass.

14. The integrated circuit structure of claim 8 , wherein the stress tuning region is in a semiconductor chip, and wherein the stress tuning region forms a ring adjacent to four edges of the semiconductor chip.

15. An integrated circuit structure comprising:
a substrate;
a first low-k dielectric layer over the substrate;
a dielectric stress tuning layer over the first low-k dielectric layer, wherein the dielectric stress tuning layer has an internal stress higher than about 4 MPa;
a metal line extending from a top surface of the dielectric stress tuning layer to a bottom surface of the first low-k dielectric layer; and
an etch stop layer comprising:
a first portion over and contacting the dielectric stress tuning layer and the metal line; and
a plurality of second portions penetrating through the dielectric stress tuning layer, wherein the plurality of second portions contacts a top surface of the first low-k dielectric layer.

16. The integrated circuit structure of claim 15 , wherein the plurality of second portions of the etch stop layer comprises a plurality of discrete portions, each encircled by the dielectric stress tuning layer, and wherein the plurality of second portions is separated from each other by the dielectric stress tuning layer.

17. The integrated circuit structure of claim 15 , wherein the plurality of second portions of the etch stop layer comprises a ring portion proximal edges of a respective chip that comprises the integrated circuit structure, with an entirety of an inner edge and an entirety of an outer edge of the ring portion contacting the dielectric stress tuning layer.

18. The integrated circuit structure of claim 15 , wherein a top surface of the metal line is coplanar with a top surface of the dielectric stress tuning layer, and a bottom surface of the metal line is coplanar with a bottom surface of the first low-k dielectric layer.

19. The integrated circuit structure of claim 15 , wherein lowest bottom surfaces of the etch stop layer are coplanar with a bottom surface of the dielectric stress tuning layer.

20. The integrated circuit structure of claim 15 further comprising a second low-k dielectric layer over and contacting the etch stop layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Yung-Yao
• Chiou Ying-Han
• Wang Ling-Sung

Classifications

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10W72/981

  Auxiliary members, e.g. spacers · CPC title