Semiconductor structures having low resistance paths throughout a wafer
US-2015332925-A1 · Nov 19, 2015 · US
US10784111B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10784111-B2 |
| Application number | US-201716345385-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 29, 2017 |
| Priority date | Oct 27, 2016 |
| Publication date | Sep 22, 2020 |
| Grant date | Sep 22, 2020 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A substrate W having a non-plateable material portion 31 and a plateable material portion 32 formed on a surface thereof is prepared, and then, a catalyst is imparted selectively to the plateable material portion 32 by supplying a catalyst solution N1 onto the substrate W. Thereafter, a plating layer 35 is selectively formed on the plateable material portion 32 by supplying a plating liquid M1 onto the substrate W. A pH of the catalyst solution N1 is previously adjusted such that the plating layer 35 is suppressed from being precipitated on the non-plateable material portion 31 while being facilitated to be precipitated on the plateable material portion 32.
Opening claim text (preview).
We claim: 1. A plating method, comprising: preparing a substrate having a non-plateable material portion and a plateable material portion formed on a surface thereof; imparting a catalyst selectively to the plateable material portion by supplying a catalyst solution onto the substrate; and forming a plating layer selectively on the plateable material portion by supplying a plating liquid onto the substrate, wherein a pH of the catalyst solution is previously adjusted to be in a pH range between isoelectric points of a main component of the non-plateable material portion and a main component of the plateable material portion such that the plating layer is suppressed from being precipitated on the non-plateable material portion while being facilitated to be precipitated on the plateable material portion. 2. A plating method, comprising: preparing a substrate having a non-plateable material portion and a plateable material portion formed on a surface thereof; imparting a catalyst selectively to the plateable material portion by supplying a catalyst solution onto the substrate; and forming a plating layer selectively on the plateable material portion by supplying a plating liquid onto the substrate, wherein a pH of the catalyst solution is previously adjusted such that the plating layer is suppressed from being precipitated on the non-plateable material portion while being facilitated to be precipitated on the plateable material portion, and wherein the non-plateable material portion is made of SiO 2 as a main component, the plateable material portion is made of SiN as a main component, and the pH falls within a range from 2 to 3. 3. The plating method of claim 1 , wherein the substrate includes a base member made of the plateable material portion and a core member which is protruded from the base member and is made of the non-plateable material portion.
Related publications grouped by family.
Answers are generated from the same data shown on this page.